[Commit-gnuradio] r6495 - gnuradio/branches/developers/matt/u2f/eth/bench/verilog

[matt]

Author: matt
Date: 2007-09-20 17:52:27 -0600 (Thu, 20 Sep 2007)
New Revision: 6495

Modified:
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbo_err.scr
   gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v
Log:
new code dump from Claus 2007_09_21


Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr   
2007-09-20 23:48:47 UTC (rev 6494)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr   
2007-09-20 23:52:27 UTC (rev 6495)
@@ -12,36 +12,42 @@
 // Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
 10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
 
+//--- Packets #0 & 1 --------------------------------------------------------
+
 // Transmit a 200-byte frame 1 time - and expect it to be received again!
 20 00 C8 00 01
 
 // Wait (indefinitely) for missing Rx packets
 22 00 00 
 
-// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
-21 00 C8 00 01
+// Transmit a 200-byte frame 1 time - but expect to receive it with error!
+25 00 C8 00 01
 
-// Inject a single bit error in the packet (data bit 0)
+// Inject a single bit error in the packet (data bit 0) - this will cause a 
CRC error
 23 00 01
 
 // Wait (indefinitely) for missing Rx packets
 22 00 00 
 
+//--- Packets #2 & 3 --------------------------------------------------------
+
 // Transmit a 200-byte frame 1 time - and expect it to be received again!
 20 00 C8 00 01
 
 // Wait (indefinitely) for missing Rx packets
 22 00 00 
 
-// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
-21 00 C8 00 01
+// Transmit a 200-byte frame 1 time - but expect to receive it with error!
+25 00 C8 00 01
 
-// Inject a single bit error in the packet (data bit 7)
+// Inject a single bit error in the packet (data bit 7) - this will cause a 
CRC error
 23 00 80
 
 // Wait (indefinitely) for missing Rx packets
 22 00 00 
 
+//--- Packets #4 & 5 --------------------------------------------------------
+
 // Transmit a 200-byte frame 1 time - and expect it to be received again!
 20 00 C8 00 01
 
@@ -51,12 +57,15 @@
 // Transmit a 200-byte frame 1 time - but don't expect it to be received again!
 21 00 C8 00 01
 
-// Inject a single bit error in the packet (RxEn)
+// Inject a single bit error in the packet (RxEn) - this will cause a packet 
discard!
+// (because it happens early in the packet)
 23 01 00
 
 // Wait (indefinitely) for missing Rx packets
 22 00 00 
 
+//--- Packets #6 & 7 --------------------------------------------------------
+
 // Transmit a 200-byte frame 1 time - and expect it to be received again!
 20 00 C8 00 01
 
@@ -72,6 +81,8 @@
 // Wait (indefinitely) for missing Rx packets
 22 00 00 
 
+//--- Packet #8 -------------------------------------------------------------
+
 // Transmit a 200-byte frame 1 time - and expect it to be received again!
 20 00 C8 00 01
 

Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbo_err.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbo_err.scr       
2007-09-20 23:48:47 UTC (rev 6494)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbo_err.scr       
2007-09-20 23:52:27 UTC (rev 6495)
@@ -13,22 +13,28 @@
 10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
 
 // Transmit a 2049-byte frame 2 times - and expect them to be received again!
-20 08 01 00 02
+20 08 02 00 02
 
 // Wait (indefinitely) for missing Rx packets
 22 00 00 
 
-// Transmit a 2049-byte frame 1 time - but don't expect it to be received 
again!
-20 08 01 00 01
+// Transmit a 2049-byte frame 1 time - but expect to receive it with error!
+25 08 02 00 01
 
 // Delay 256 NOPs to time the error injection to be late in the packet
 0F 01 00
 
 // Inject a single bit error in the packet (data bit 0)
-23 00 01
+23 01 00
 
 // Wait (indefinitely) for missing Rx packets
 22 00 00 
 
+// Transmit a 2049-byte frame 2 times - and expect them to be received again!
+20 08 01 00 02
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00 
+
 // Halt
 FF

Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v    
2007-09-20 23:48:47 UTC (rev 6494)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v    
2007-09-20 23:52:27 UTC (rev 6495)
@@ -90,6 +90,7 @@
   wire [1:0]  Rx_mac_BE;
   wire        Rx_mac_pa;
   wire        Rx_mac_sop;
+  wire        Rx_mac_err;
   wire        Rx_mac_eop;
 
   // User interface (Tx)
@@ -151,6 +152,7 @@
     .Rx_mac_BE  ( Rx_mac_BE   ),
     .Rx_mac_pa  ( Rx_mac_pa   ),
     .Rx_mac_sop ( Rx_mac_sop  ),
+    .Rx_mac_err ( Rx_mac_err  ),
     .Rx_mac_eop ( Rx_mac_eop  ),
 
     .Tx_mac_wa  ( Tx_mac_wa   ),
@@ -413,6 +415,7 @@
   task SendPacket;
     input [15:0] Length;
     input        Wr2FIFO;
+    input        Ignore;
 
     reg [15:0] Counter;
     integer    TxIndex;
@@ -467,10 +470,18 @@
 
           if ( Wr2FIFO )
             begin
-//              if ( (TxPacketCount == 3) && (Counter <= 4) )
-//                FIFO_Wr( { Tx_mac_sop, Tx_mac_eop, Tx_mac_BE, Tx_mac_data ^ 
32'h01000000 } );
-//              else
-                FIFO_Wr( { Tx_mac_sop, Tx_mac_eop, Tx_mac_BE, Tx_mac_data } );
+              if ( Ignore )
+                begin
+                  FIFO_Wr( { 2'b11, 2'b00, 32'h00000000 } );
+                  Wr2FIFO = 0;
+                end
+              else
+                begin
+//                if ( (TxPacketCount == 3) && (Counter <= 4) )
+//                  FIFO_Wr( { Tx_mac_sop, Tx_mac_eop, Tx_mac_BE, Tx_mac_data 
^ 32'h01000000 } );
+//                else
+                  FIFO_Wr( { Tx_mac_sop, Tx_mac_eop, Tx_mac_BE, Tx_mac_data } 
);
+                end
             end
 
           Tx_mac_wr = 1;
@@ -509,6 +520,7 @@
 
   reg     InPacket;
   integer RxPacketLength;
+  reg     IgnoreUntilNextERR;
 
    always @( posedge Clk_user or posedge Reset )
     if ( Reset )
@@ -516,6 +528,7 @@
         InPacket = 0;
         RxPacketCount = 0;
         Negate_Rx_mac_rd <= 0;
+        IgnoreUntilNextERR = 0;
       end
     else
       begin
@@ -536,8 +549,21 @@
             endcase
 
             // Retrieve expected packet data
-            FIFO_Rd( Expected );
 
+            if ( !IgnoreUntilNextERR )
+              begin
+                FIFO_Rd( Expected );
+                if ( Expected[35] & Expected[34] )
+                  begin
+                    // Both SOP & EOP are asserted in expectancy data
+                    // - this means that we should ignore all data received 
until next EOP
+                    $display( "The payload of this packet will be IGNORED - 
and an ERROR must be signalled!" );
+                    IgnoreUntilNextERR = 1;
+                  end
+              end
+            if ( IgnoreUntilNextERR )
+              Mask = 36'h000000000;
+
             //$display( "DEBUG: RxData=0x%0x, Expected=0x%0x", RxData, 
Expected );
 
             if ( (RxData & Mask) !== (Expected & Mask) )
@@ -583,6 +609,23 @@
                     Error = 1;
                   end
               end
+
+            if ( Rx_mac_err )
+              begin
+                if ( !Rx_mac_eop )
+                  begin
+                    $display( "ERROR: Rx_mac_err was asserted without 
Rx_mac_eop also being asserted!" );
+                    Error = 1;
+                  end
+                if ( IgnoreUntilNextERR )
+                  $display( "Info: Rx_mac_err was asserted as expected!" );
+                else
+                  begin
+                    $display( "ERROR: Rx_mac_err was unexpectedly asserted!" );
+                    Error = 1;
+                  end
+                IgnoreUntilNextERR = 0;
+              end
           end
       end
 
@@ -640,10 +683,11 @@
   task ScriptSendPacket;
     input [15:0] Length;
     input        ExpectToRx;
+    input        Ignore;
 
     begin
-      $display( "ScriptSendPacket( 0x%04x, %0d )", Length, ExpectToRx );
-      SendPacket( Length, ExpectToRx );
+      $display( "ScriptSendPacket( 0x%04x, %0d, %0d )", Length, ExpectToRx, 
Ignore );
+      SendPacket( Length, ExpectToRx, Ignore );
       if ( ExpectToRx )
         RxExpectPacketCount = RxExpectPacketCount + 1;
     end
@@ -747,7 +791,7 @@
                 Count  = Get16bit(i); // Number of times
                 while ( Count != 0 )
                   begin
-                    ScriptSendPacket( Length, 1 );
+                    ScriptSendPacket( Length, 1, 0 );
                     Count = Count - 1;
                   end
               end
@@ -758,7 +802,7 @@
                 Count  = Get16bit(i); // Number of times
                 while ( Count != 0 )
                   begin
-                    ScriptSendPacket( Length, 0 );
+                    ScriptSendPacket( Length, 0, 0 );
                     Count = Count - 1;
                   end
               end
@@ -824,6 +868,17 @@
                 FIFO_Wr( { 1'b0, 1'b1, 2'b00, 32'h00000000 } );
               end
 
+            8'h25: // Transmit packet - and indicate that it must be IGNORED 
upon reception
+              begin
+                Length = Get16bit(i); // Length in bytes
+                Count  = Get16bit(i); // Number of times
+                while ( Count != 0 )
+                  begin
+                    ScriptSendPacket( Length, 1, 1 );
+                    Count = Count - 1;
+                  end
+              end
+
             8'hff: // Halt
               begin
                 $display( "HALT" );