[Commit-gnuradio] r6494 - gnuradio/branches/developers/matt/u2f/eth

[matt]

Author: matt
Date: 2007-09-20 17:48:47 -0600 (Thu, 20 Sep 2007)
New Revision: 6494

Modified:
   gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v
Log:
seems to basically work


Modified: gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v  2007-09-20 
23:47:15 UTC (rev 6493)
+++ gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v  2007-09-20 
23:48:47 UTC (rev 6494)
@@ -37,7 +37,13 @@
    //  We are allowed to do one more write after we are told the FIFO is full
    //  This allows us to register the _wa signal and speed up timing.
 
-   assign      Rx_mac_rd = 0;
+   reg                rx_mac_ra_d1;
+   always @(posedge clk)
+     if(rst) rx_mac_ra_d1 <= 0;
+     else rx_mac_ra_d1 <= Rx_mac_ra;
+   
+   assign      Rx_mac_rd = rx_mac_ra_d1 & ~full;
+   assign      sfifo_write = Rx_mac_pa;  // We need to write even if we didn't 
ask for the data...
    assign      sfifo_in = {Rx_mac_error,Rx_mac_sop,Rx_mac_eop,Rx_mac_data};
    
    // BUFFER side signals
@@ -72,9 +78,8 @@
    assign wr_dat_o = sfifo_out[31:0];
    assign wr_write_o = xfer_active & ~empty;
    assign wr_done_o = eop & ~empty;    // FIXME double check this
-   assign wr_error_o = error | (wr_full & ~eop);  // FIXME potential timing 
problem
+   assign wr_error_o = error | (wr_full_i & ~eop);  // FIXME potential timing 
problem
 
    // How do we handle wr_full_i?
    
 endmodule // mac_rxfifo_int
-