[Commit-gnuradio] r6437 - gnuradio/branches/developers/matt/u2f/eth

[matt]

Author: matt
Date: 2007-09-13 21:40:45 -0600 (Thu, 13 Sep 2007)
New Revision: 6437

Modified:
   gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v
   gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v
Log:
first cut at interfacing to the new buffer interface


Modified: gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v  2007-09-14 
03:40:05 UTC (rev 6436)
+++ gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v  2007-09-14 
03:40:45 UTC (rev 6437)
@@ -9,6 +9,7 @@
    input Rx_mac_pa,
    input Rx_mac_sop,
    input Rx_mac_eop,
+   input Rx_mac_error,
 
    output [31:0] wr_dat_o,
    output wr_write_o,
@@ -22,25 +23,58 @@
    // 00 means all 4 bytes are valid, 01 means 1 byte (bit 31:24), 10 means 2 
bytes, 11 means 3 bytes. 
    // This goes for both Tx and Rx direction. 
 
-   shortfifo #(.WIDTH(32)) rxmac_sfifo
+
+   // Might as well use a shortfifo here since they are basically free
+   wire  empty, full, sfifo_write, sfifo_read;
+   wire [34:0] sfifo_in, sfifo_out;
+   
+   shortfifo #(.WIDTH(35)) txmac_sfifo
      (.clk(clk),.rst(rst),
-      .datain(Rx_mac_data),.write(Rx_mac_rd),.full(full),
-      .dataout(wr_dat_o),.read(wr_write_o),.empty(empty));
+      .datain(sfifo_in),.write(sfifo_write),.full(full),
+      .dataout(sfifo_out),.read(sfifo_read),.empty(empty));
+   
+   // MAC side signals
+   //  We are allowed to do one more write after we are told the FIFO is full
+   //  This allows us to register the _wa signal and speed up timing.
 
-   reg          in_packet;
+   assign      Rx_mac_rd = 0;
+   assign      sfifo_in = {Rx_mac_error,Rx_mac_sop,Rx_mac_eop,Rx_mac_data};
    
+   // BUFFER side signals
+   reg                xfer_active, error_active;
+   wire        sop, eop, error;
+   
+   assign      sop = sfifo_out[33];
+   assign      eop = sfifo_out[32];
+   assign      error = sfifo_out[34];
+   
    always @(posedge clk)
      if(rst)
-       in_packet <= 0;
-     else if(Rx_mac_sop)
-       in_packet <= 1;
-     else if(Rx_mac_eop)
-       in_packet <= 0;
-     else if(wr_error_o)
-       in_packet <= 0;
+       begin
+         xfer_active <= 0;
+         error_active <= 0;
+       end
+     else if(eop)
+       begin
+         xfer_active <= 0;
+         error_active <=0;
+       end
+     else if(error | wr_full_i)
+       begin
+         xfer_active <= 0;
+         error_active <= 1;
+       end
+     else if(wr_ready_i & ~error_active)
+       xfer_active <= 1;
 
-   wire  write_into_sfifo = 0;
-   wire  read_from_macfifo = 0;
-       
+   assign sfifo_read = (error_active | xfer_active) & ~empty;
+   
+   assign wr_dat_o = sfifo_out[31:0];
+   assign wr_write_o = xfer_active & ~empty;
+   assign wr_done_o = eop & ~empty;    // FIXME double check this
+   assign wr_error_o = error | (wr_full & ~eop);  // FIXME potential timing 
problem
+
+   // How do we handle wr_full_i?
+   
 endmodule // mac_rxfifo_int
 

Modified: gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v  2007-09-14 
03:40:05 UTC (rev 6436)
+++ gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v  2007-09-14 
03:40:45 UTC (rev 6437)
@@ -1,52 +1,66 @@
 
 module mac_txfifo_int
   (input clk, input rst,
-   
+
+   // To MAC
    input Tx_mac_wa,
    output Tx_mac_wr,
    output [31:0] Tx_mac_data,
    output [1:0] Tx_mac_BE,
    output Tx_mac_sop,
    output Tx_mac_eop,
-   
+
+   // To buffer interface
    input [31:0] rd_dat_i,
    output rd_read_o,
    output rd_done_o,
    output rd_error_o,
-   input rd_ready_i,
-   input rd_empty_i);
+   input rd_sop_i,
+   input rd_eop_i);
    
+   
+   // Might as well use a shortfifo here since they are basically free
+   wire  empty, full, sfifo_write, sfifo_read;
+   wire [33:0] sfifo_in, sfifo_out;
+   
+   shortfifo #(.WIDTH(34)) txmac_sfifo
+     (.clk(clk),.rst(rst),
+      .datain(sfifo_in),.write(sfifo_write),.full(full),
+      .dataout(sfifo_out),.read(sfifo_read),.empty(empty));
+   
+   // MAC side signals
    //  We are allowed to do one more write after we are told the FIFO is full
    //  This allows us to register the _wa signal and speed up timing.
    
-   reg          tx_mac_wa_d1;
+   reg                tx_mac_wa_d1;
    always @(posedge clk)
      tx_mac_wa_d1 <= Tx_mac_wa;
    
-   //assign Tx_mac_data = rd_dat_i;
-   //assign Tx_mac_eop = rd_empty_i;
-   
-   // From Claus -- 
-   // The _BE fields are only valid when _eop is asserted. 
-   // 00 means all 4 bytes are valid, 01 means 1 byte (bit 31:24), 10 means 2 
bytes, 11 means 3 bytes. 
-   // This goes for both Tx and Rx direction. 
+   assign      sfifo_read = ~empty & tx_mac_wa_d1;
 
-   assign Tx_mac_BE = 0;  // Since we only deal with packets that are 
multiples of 32 bits long
+   assign      Tx_mac_wr = sfifo_read;
+   assign      Tx_mac_data = sfifo_out[31:0];
+   assign      Tx_mac_BE = 0;  // Since we only deal with packets that are 
multiples of 32 bits long
+   assign      Tx_mac_sop = sfifo_out[33];
+   assign      Tx_mac_eop = sfifo_out[32];
 
-   // Might as well use a shortfifo here since they are basically free
-   wire   empty, full;
-   assign Tx_mac_wr = ~empty & tx_mac_wa_d1;
-   assign rd_read_o = ~full & rd_ready_i;
+
+   // BUFFER side signals
+   reg                xfer_active;
+   always @(posedge clk)
+     if(rst)
+       xfer_active <= 0;
+     else if(rd_eop_i & ~full)
+       xfer_active <= 0;
+     else if(rd_sop_i)
+       xfer_active <= 1;
    
-   shortfifo #(.WIDTH(32)) txmac_sfifo
-     (.clk(clk),.rst(rst),
-      .datain(rd_dat_i),.write(rd_read_o),.full(full),
-      .dataout(Tx_mac_data),.read(Tx_mac_wr),.empty(empty));
+   assign      sfifo_in = {rd_sop_i, rd_eop_i, rd_dat_i};
+   assign      sfifo_write = xfer_active & ~full;
 
-   // need to control sop and eop
-
-   assign rd_error_o = 0;  // No possible error situations?
-   assign rd_done_o = 0;  // Always send everything we're given?
+   assign      rd_read_o = sfifo_write;
+   assign      rd_done_o = 0;  // Always send everything we're given?
+   assign      rd_error_o = 0;  // No possible error situations?
    
 endmodule // mac_txfifo_int