[Commit-gnuradio] r6436 - gnuradio/branches/developers/matt/u2f/sdr_lib

[matt]

Author: matt
Date: 2007-09-13 21:40:05 -0600 (Thu, 13 Sep 2007)
New Revision: 6436

Added:
   gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v
   gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v
Modified:
   gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v
   gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
Log:
split out buffering and control from the actual dsp core


Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v 2007-09-14 
03:39:24 UTC (rev 6435)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v 2007-09-14 
03:40:05 UTC (rev 6436)
@@ -7,16 +7,14 @@
    input [13:0] adc_a, input adc_ovf_a,
    input [13:0] adc_b, input adc_ovf_b,
    
-   output [31:0] rx_dat_o,
-   output rx_write_o,
-   output rx_done_o,
-   output rx_error_o,
-   input rx_ready_i,
-   input rx_full_i,
-   output overrun
+   output [15:0] bb_i,
+   output [15:0] bb_q,
+   input run_rx,
+   output wr_req
    );
 
-   assign rx_error_o = 0;
+   assign bb_i = i_decim;
+   assign bb_q = q_decim;
    
    wire [15:0] scale_i, scale_q;
    wire [31:0] phase_inc;
@@ -25,8 +23,6 @@
    wire [23:0] i_decim, q_decim;
    wire [7:0]  decim_rate;
 
-   wire        run_rx;
-   
    setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
@@ -39,10 +35,6 @@
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(decim_rate),.changed());
 
-   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(run_rx),.changed());
-
    always @(posedge clk)
      if(rst)
        phase <= 0;
@@ -69,13 +61,4 @@
              .rate(decim_rate),.strobe_in(1'b1),.strobe_out(stb_decim),
              .signal_in(q_bb),.signal_out(q_decim));
    
-   wire        full, empty;
-   assign      rx_done_o = 0;
-   assign      rx_write_o = rx_ready_i & ~empty;   // FIXME potential critical 
path
-   assign      overrun = full & stb_decim;
-   
-   longfifo #(.WIDTH(32),.SIZE(9)) rxfifo
-     
(.clk(clk),.rst(rst),.datain({q_decim[23:8],i_decim[23:8]}),.dataout(rx_dat_o),
-      .read(rx_write_o),.write(stb_decim & ~full),.full(full),.empty(empty));
-   
 endmodule // dsp_core_rx

Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-09-14 
03:39:24 UTC (rev 6435)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-09-14 
03:40:05 UTC (rev 6436)
@@ -7,23 +7,19 @@
 
    output reg [15:0] dac_a,
    output reg [15:0] dac_b,
-   
-   input [31:0] tx_dat_i,
-   output tx_read_o,
-   output tx_done_o,
-   output tx_error_o,
-   input tx_ready_i,
-   input tx_empty_i,
-   output underrun
-   );
 
-   assign tx_error_o = 0;
+   // To tx_control
+   input [15:0] bb_i,
+   input [15:0] bb_q,
+   input run_tx,
+   output rd_ack  // asserting rd_ack means "I got it, send the next one"
+   );
+   
    wire [15:0] i, q, scale_i, scale_q;
    wire [31:0] phase_inc;
    reg [31:0]  phase;
    wire [7:0]  interp_rate;
    wire        stb_interp;
-   wire        run_tx;
    
    setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -36,53 +32,40 @@
    setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(interp_rate),.changed());
-
-   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(run_tx),.changed());
-
-   wire        full, empty;
-   assign      tx_done_o = 0;
-   assign      tx_read_o = tx_ready_i & ~full;  // FIXME potential critical 
path
-   assign      underrun = empty & stb_interp;
-
-   wire        enable_tx = run_tx; 
    
-   longfifo #(.WIDTH(32),.SIZE(9)) txfifo
-     (.clk(clk),.rst(rst),.datain(tx_dat_i),.dataout({q,i}),
-      .read(stb_interp & ~empty),.write(tx_read_o),.full(full),.empty(empty));
-
    strobe_gen 
strobe_gen(.clock(clk),.reset(rst),.enable(run_tx),.rate(interp_rate),
-                        .strobe_in(enable_tx),.strobe(stb_interp) );
+                        .strobe_in(run_tx),.strobe(stb_interp) );
    
+   assign      rd_ack = stb_interp;
+   
    always @(posedge clk)
      if(rst)
        phase <= 0;
      else if(run_tx)
        phase <= phase + phase_inc;
-
-   wire         signed [15:0]   da, db;
-   reg                  signed [15:0]   dar, dbr;
    
-   wire         signed [35:0] prod_i, prod_q;
-
-   wire [15:0]          i_interp, q_interp;
+   wire        signed [15:0] da, db;
+   reg                signed [15:0] dar, dbr;
    
+   wire        signed [35:0] prod_i, prod_q;
+   
+   wire [15:0] i_interp, q_interp;
+   
    cic_interp  #(.bw(16),.N(4),.log2_of_max_rate(7))
-     
cic_interp_i(.clock(clk),.reset(rst),.enable(enable_tx),.rate(interp_rate),
+     cic_interp_i(.clock(clk),.reset(rst),.enable(run_tx),.rate(interp_rate),
                  .strobe_in(stb_interp),.strobe_out(1),
-                 .signal_in(empty ? 0 : i),.signal_out(i_interp));
+                 .signal_in(bb_i),.signal_out(i_interp));
    
    cic_interp  #(.bw(16),.N(4),.log2_of_max_rate(7))
-     
cic_interp_q(.clock(clk),.reset(rst),.enable(enable_tx),.rate(interp_rate),
+     cic_interp_q(.clock(clk),.reset(rst),.enable(run_tx),.rate(interp_rate),
                  .strobe_in(stb_interp),.strobe_out(1),
-                 .signal_in(empty ? 0 : q),.signal_out(q_interp));
+                 .signal_in(bb_q),.signal_out(q_interp));
    
    cordic #(.bitwidth(16),.zwidth(16))
-     cordic(.clock(clk), .reset(rst), .enable(enable_tx),
+     cordic(.clock(clk), .reset(rst), .enable(run_tx),
            .xi(i_interp),.yi(q_interp),.zi(phase[31:16]),
            .xo(da),.yo(db),.zo() );
-
+   
    MULT18X18S MULT18X18S_inst 
      (.P(prod_i),    // 36-bit multiplier output
       .A({{2{da[15]}},da} ),    // 18-bit multiplier input
@@ -103,7 +86,7 @@
    
    always @(posedge clk)
      dac_a <= prod_i[23:8];
-
+   
    always @(posedge clk)
      dac_b <= prod_q[23:8];
    

Added: gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v                  
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v  2007-09-14 
03:40:05 UTC (rev 6436)
@@ -0,0 +1,61 @@
+
+
+module rx_control
+  #(parameter FIFOSIZE = 10)
+    (input clk, input rst,
+     input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     
+     input [31:0] master_time,
+     
+     // To Buffer interface
+     output [31:0] wr_dat_o,
+     output wr_write_o,
+     output wr_done_o,
+     output wr_error_o,
+
+     input wr_ready_i,
+     input wr_full_i,
+     
+     // From DSP Core
+     input [15:0] bb_i,
+     input [15:0] bb_q,
+     output run_rx,
+     input wr_req
+     
+     );
+
+   // Buffer interface to internal FIFO
+   wire    write, full, read, empty;
+   reg            xfer_active;
+
+   always @(posedge clk)
+     if(rst)
+       xfer_active <= 0;
+     else if(eop_o | wr_full_i)
+       xfer_active <= 0;
+     else if(wr_ready_i)
+       xfer_active <= 1;
+   
+   assign  read = xfer_active & ~empty;
+   
+   assign  wr_write_o = read;
+   assign  wr_done_o = eop_o & ~empty;
+   assign  wr_error_o = 0;
+   
+   // Internal FIFO, size 9 is 2K, size 10 is 4K
+   longfifo #(.WIDTH(34),.SIZE(FIFOSIZE)) rxfifo
+     (.clk(clk),.rst(rst),
+      .datain({sop_i,eop_i,bb_i,bb_q}), .write(write), .full(full),
+      .dataout({sop_o,eop_o,wr_dat_o}), .read(read), .empty(empty)
+      );
+
+   // Internal FIFO to DSP interface
+   
+   //     Inband signalling support needs to go in here...
+   assign  run_rx = ~full;
+   assign  write = wr_req & ~full;
+
+   wire    overrun = wr_req & full;
+   
+endmodule // rx_control
+

Added: gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v                  
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v  2007-09-14 
03:40:05 UTC (rev 6436)
@@ -0,0 +1,59 @@
+
+
+module tx_control
+  #(parameter FIFOSIZE = 10)
+    (input clk, input rst,
+     input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     
+     input [31:0] master_time,
+     
+     // To Buffer interface
+     input [31:0] rd_dat_i,
+     input rd_sop_i,
+     input rd_eop_i,
+     output rd_read_o,
+     output rd_done_o,
+     output rd_error_o,
+     
+     // To DSP Core
+     output [15:0] bb_i,
+     output [15:0] bb_q,
+     output run_tx,
+     input rd_ack
+     
+     );
+
+   // Buffer interface to internal FIFO
+   wire    write, full, read, empty;
+   reg            xfer_active;
+   always @(posedge clk)
+     if(rst)
+       xfer_active <= 0;
+     else if(rd_eop_i & ~full)  // In case the last line can't be stored right 
away
+       xfer_active <= 0;
+     else if(rd_sop_i)
+       xfer_active <= 1;
+   
+   assign  write = xfer_active & ~full;
+   
+   assign  rd_read_o = write;
+   assign  rd_done_o = 0;  // Always take everything we're given
+   assign  rd_error_o = 0;  // Don't anticipate any errors here
+   
+   // Internal FIFO, size 9 is 2K, size 10 is 4K
+   wire    sop_o, eop_o;
+   longfifo #(.WIDTH(34),.SIZE(FIFOSIZE)) txfifo
+     (.clk(clk),.rst(rst),
+      .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full),
+      .dataout({sop_o,eop_o,bb_i,bb_q}), .read(read), .empty(empty)
+      );
+
+   // Internal FIFO to DSP interface
+   
+   //     Inband signalling support needs to go in here...
+   assign  run_tx = ~empty;
+   assign  read = rd_ack & ~empty;
+
+   wire    underrun = rd_ack & empty;
+   
+endmodule // tx_control