[Commit-gnuradio] r6435 - gnuradio/branches/developers/matt/u2f/top/u2_basic

[matt]

Author: matt
Date: 2007-09-13 21:39:24 -0600 (Thu, 13 Sep 2007)
New Revision: 6435

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
misc port width fixes, start of changes to buffer interfaces


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-09-14 03:33:49 UTC (rev 6434)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-09-14 03:39:24 UTC (rev 6435)
@@ -1,4 +1,4 @@
-//////////////////////////////////////////////////////////////////////////////////
+ 
//////////////////////////////////////////////////////////////////////////////////
 // Module Name:    u2_basic
 
//////////////////////////////////////////////////////////////////////////////////
 
@@ -229,17 +229,17 @@
             
.iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? 
iram_rd_stb : iram_wr_stb),
             .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel),
             
-            .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i),
+            .dwb_adr_i(s0_adr[13:0]),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i),
             
.dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel));
 
    assign       s0_err = 1'b0;
    assign       s0_rty = 1'b0;
 
    // Buffer Pool, slave #1
-   wire         rd0_read, rd0_ready, rd0_error, rd0_done, rd0_empty;
-   wire         rd1_read, rd1_ready, rd1_error, rd1_done, rd1_empty;
-   wire         rd2_read, rd2_ready, rd2_error, rd2_done, rd2_empty;
-   wire         rd3_read, rd3_ready, rd3_error, rd3_done, rd3_empty;
+   wire         rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
+   wire         rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
+   wire         rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop;
+   wire         rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop;
    wire [31:0]          rd0_dat, rd1_dat, rd2_dat, rd3_dat;
 
    wire         wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full;
@@ -271,18 +271,18 @@
       .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full),
       // Read Interfaces
       .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done),
-      .rd0_error_i(rd0_error), .rd0_ready_o(rd0_ready), 
.rd0_empty_o(rd0_empty),
+      .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop),
       .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done),
-      .rd1_error_i(rd1_error), .rd1_ready_o(rd1_ready), 
.rd1_empty_o(rd1_empty),
+      .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop),
       .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done),
-      .rd2_error_i(rd2_error), .rd2_ready_o(rd2_ready), 
.rd2_empty_o(rd2_empty),
+      .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop),
       .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done),
-      .rd3_error_i(rd3_error), .rd3_ready_o(rd3_ready), .rd3_empty_o(rd3_empty)
+      .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop)
       );
 
    // SPI -- Slave #2
    spi_top shared_spi
-     
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
+     
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
       
.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),
 
       .wb_err_o(s2_err),.wb_int_o(s2_int),
@@ -294,12 +294,13 @@
    // I2C -- Slave #3
    i2c_master_top #(.ARST_LVL(1)) 
      i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
-         .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i),
+         
.wb_adr_i(s3_adr[2:0]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
          .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
          .wb_ack_o(s3_ack),.wb_inta_o(s3_int),
          
.scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
          
.sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
-   
+
+   assign       s3_dat_i[31:8] = 24'd0;
    assign       s3_err = 1'b0;
    assign       s3_rty = 1'b0;
    
@@ -387,7 +388,7 @@
    wire [1:0]   Tx_mac_BE, Rx_mac_BE;
    
    MAC_top MAC_top
-     (.Clk_125M(),.Clk_user(dsp_clk),.Speed(),
+     (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),.Speed(),
       
.RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
       
.WE_I(s6_we),.DAT_I(s6_dat_o[15:0]),.DAT_O(s6_dat_i[15:0]),.ACK_O(s6_ack),
       .Rx_mac_ra(Rx_mac_ra),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
@@ -415,13 +416,17 @@
       .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
       .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
       .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
-      .rd_error_o(rd2_error),.rd_ready_i(rd2_ready),.rd_empty_i(rd2_empty) );
+      .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop) );
 
 
    // /////////////////////////////////////////////////////////////////////////
    // DSP
    reg [13:0]   adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
    reg                  adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, 
adc_ovf_b_reg2;
+
+   wire [15:0]          bb_i_tx, bb_q_tx, bb_i_rx, bb_q_rx;
+   wire         run_rx, run_tx;
+   wire         wr_req, rd_ack;
    
    always @(posedge dsp_clk)
      begin
@@ -434,23 +439,35 @@
        adc_ovf_b_reg1 <= adc_ovf_b;
        adc_ovf_b_reg2 <= adc_ovf_b_reg1;
      end // always @ (posedge dsp_clk)
+
+   rx_control rx_control
+     (.clk(dsp_clk), .rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .master_time(),
+      .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), 
.wr_error_o(wr1_error),
+      .wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
+      .bb_i(bb_i_rx), .bb_q(bb_q_rx), .run_rx(run_rx), .wr_req(wr_req) );
    
    dsp_core_rx dsp_core_rx
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
-      
.rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done),.rx_error_o(wr1_error),
-      .rx_ready_i(wr1_ready),.rx_full_i(wr1_full),
-      .overrun() );
+      .bb_i(bb_i_rx), .bb_q(bb_q_rx), .run_rx(run_rx), .wr_req(wr_req) );
+
+   tx_control tx_control
+     (.clk(dsp_clk), .rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .master_time()
+      .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop),
+      .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error),
+      .bb_i(bb_i_tx), .bb_q(bb_q_tx), .run_tx(run_tx), .rd_ack(rd_ack) );
    
    dsp_core_tx dsp_core_tx
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .dac_a(dac_a),.dac_b(dac_b),
-      
.tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done),.tx_error_o(rd1_error),
-      .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty),
-      .underrun() );
-   
+      .bb_i(bb_i_tx), .bb_q(bb_q_tx), .run_tx(run_tx), .rd_ack(rd_ack) );
+
    assign dsp_rst = wb_rst;
 
    // 
///////////////////////////////////////////////////////////////////////////////////
@@ -459,7 +476,7 @@
      (.clk(dsp_clk),.rst(dsp_rst),
       
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
       
.fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done),.fifo_error_o(rd0_error),
-      .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty)
+      .fifo_sop_i(rd0_sop),.fifo_eop_i(rd0_eop)
       );
    
    serdes_rx serdes_rx