[Commit-gnuradio] r6438 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-09-13 21:57:52 -0600 (Thu, 13 Sep 2007)
New Revision: 6438

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
Log:
port renaming for sop/eop


Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-09-14 03:40:45 UTC (rev 6437)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-09-14 03:57:52 UTC (rev 6438)
@@ -2,7 +2,7 @@
 // Buffer pool.  Contains 8 buffers, each 2K (512 by 32).  Each buffer
 // is a dual-ported RAM.  Port A on each of them is indirectly connected 
 // to the wishbone bus by a bridge.  Port B may be connected any one of the
-// 6 FIFO-like streaming interaces, or disconnected.  The wishbone bus
+// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected.  The 
wishbone bus
 // provides access to all 8 buffers, and also controls the connections
 // between the ports and the buffers, allocating them as needed.
 
@@ -40,10 +40,10 @@
    input [31:0] wr3_dat_i, input wr3_write_i, input wr3_done_i, input 
wr3_error_i, output wr3_ready_o, output wr3_full_o,
    
    // Read Interfaces
-   output [31:0] rd0_dat_o, input rd0_read_i, input rd0_done_i, input 
rd0_error_i, output rd0_ready_o, output rd0_empty_o,
-   output [31:0] rd1_dat_o, input rd1_read_i, input rd1_done_i, input 
rd1_error_i, output rd1_ready_o, output rd1_empty_o,
-   output [31:0] rd2_dat_o, input rd2_read_i, input rd2_done_i, input 
rd2_error_i, output rd2_ready_o, output rd2_empty_o,
-   output [31:0] rd3_dat_o, input rd3_read_i, input rd3_done_i, input 
rd3_error_i, output rd3_ready_o, output rd3_empty_o
+   output [31:0] rd0_dat_o, input rd0_read_i, input rd0_done_i, input 
rd0_error_i, output rd0_sop_o, output rd0_eop_o,
+   output [31:0] rd1_dat_o, input rd1_read_i, input rd1_done_i, input 
rd1_error_i, output rd1_sop_o, output rd1_eop_o,
+   output [31:0] rd2_dat_o, input rd2_read_i, input rd2_done_i, input 
rd2_error_i, output rd2_sop_o, output rd2_eop_o,
+   output [31:0] rd3_dat_o, input rd3_read_i, input rd3_done_i, input 
rd3_error_i, output rd3_sop_o, output rd3_eop_o
    );
 
    wire [7:0]   sel_a;
@@ -83,8 +83,8 @@
    wire [7:0]   rd_read_i;
    wire [7:0]   rd_done_i;
    wire [7:0]   rd_error_i;
-   wire [7:0]   rd_ready_o;
-   wire [7:0]   rd_empty_o;
+   wire [7:0]   rd_sop_o;
+   wire [7:0]   rd_eop_o;
    
    assign       status = {16'd0,error[7:0],done[7:0]};
 
@@ -157,8 +157,8 @@
              .rd_read_i(rd_read_i[i]),
              .rd_done_i(rd_done_i[i]),
              .rd_error_i(rd_error_i[i]),
-             .rd_ready_o(rd_ready_o[i]),
-             .rd_empty_o(rd_empty_o[i]) 
+             .rd_sop_o(rd_sop_o[i]),
+             .rd_eop_o(rd_eop_o[i]) 
              );
 
           // FIXME -- if it is a problem, maybe we don't need enables on these 
muxes
@@ -240,67 +240,66 @@
                   .i5(wr_full_o[5]), .i6(wr_full_o[6]), 
.i7(wr_full_o[7]),.o(wr3_full_o));
    
    mux8 #(.WIDTH(1)) 
-     mux8_rd_ready0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), 
.i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
-                   .i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
-                   .i5(rd_ready_o[5]), .i6(rd_ready_o[6]), 
.i7(rd_ready_o[7]),.o(rd0_ready_o));
+     mux8_rd_sop0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), 
.i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
+                 .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
+                 .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), 
.i7(rd_sop_o[7]),.o(rd0_sop_o));
    
    mux8 #(.WIDTH(1)) 
-     mux8_rd_empty0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), 
.i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
-                   .i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
-                   .i5(rd_empty_o[5]), .i6(rd_empty_o[6]), 
.i7(rd_empty_o[7]),.o(rd0_empty_o));
-
+     mux8_rd_eop0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), 
.i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
+                 .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
+                 .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), 
.i7(rd_eop_o[7]),.o(rd0_eop_o));
+   
    mux8 #(.WIDTH(32))
      mux8_rd_dat_0 (.en(~read_src[0][3]),.sel(read_src[0][2:0]), 
.i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
                    .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
                    .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), 
.i7(rd_dat_o[7]),.o(rd0_dat_o));
-
+   
    mux8 #(.WIDTH(1)) 
-     mux8_rd_ready1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), 
.i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
-                   .i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
-                   .i5(rd_ready_o[5]), .i6(rd_ready_o[6]), 
.i7(rd_ready_o[7]),.o(rd1_ready_o));
-
+     mux8_rd_sop1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), 
.i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
+                 .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
+                 .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), 
.i7(rd_sop_o[7]),.o(rd1_sop_o));
+   
    mux8 #(.WIDTH(1)) 
-     mux8_rd_empty1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), 
.i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
-                   .i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
-                   .i5(rd_empty_o[5]), .i6(rd_empty_o[6]), 
.i7(rd_empty_o[7]),.o(rd1_empty_o));
-
+     mux8_rd_eop1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), 
.i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
+                 .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
+                 .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), 
.i7(rd_eop_o[7]),.o(rd1_eop_o));
+   
    mux8 #(.WIDTH(32))
      mux8_rd_dat_1 (.en(~read_src[1][3]),.sel(read_src[1][2:0]), 
.i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
                    .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
                    .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), 
.i7(rd_dat_o[7]),.o(rd1_dat_o));
    
    mux8 #(.WIDTH(1)) 
-     mux8_rd_ready2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), 
.i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
-                   .i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
-                   .i5(rd_ready_o[5]), .i6(rd_ready_o[6]), 
.i7(rd_ready_o[7]),.o(rd2_ready_o));
-
+     mux8_rd_sop2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), 
.i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
+                 .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
+                 .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), 
.i7(rd_sop_o[7]),.o(rd2_sop_o));
+   
    mux8 #(.WIDTH(1)) 
-     mux8_rd_empty2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), 
.i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
-                   .i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
-                   .i5(rd_empty_o[5]), .i6(rd_empty_o[6]), 
.i7(rd_empty_o[7]),.o(rd2_empty_o));
-
+     mux8_rd_eop2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), 
.i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
+                 .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
+                 .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), 
.i7(rd_eop_o[7]),.o(rd2_eop_o));
+   
    mux8 #(.WIDTH(32))
      mux8_rd_dat_2 (.en(~read_src[2][3]),.sel(read_src[2][2:0]), 
.i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
                    .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
                    .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), 
.i7(rd_dat_o[7]),.o(rd2_dat_o));
    
    mux8 #(.WIDTH(1)) 
-     mux8_rd_ready3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), 
.i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
-                   .i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
-                   .i5(rd_ready_o[5]), .i6(rd_ready_o[6]), 
.i7(rd_ready_o[7]),.o(rd3_ready_o));
-
+     mux8_rd_sop3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), 
.i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
+                 .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
+                 .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), 
.i7(rd_sop_o[7]),.o(rd3_sop_o));
+   
    mux8 #(.WIDTH(1)) 
-     mux8_rd_empty3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), 
.i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
-                   .i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
-                   .i5(rd_empty_o[5]), .i6(rd_empty_o[6]), 
.i7(rd_empty_o[7]),.o(rd3_empty_o));
-
+     mux8_rd_eop3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), 
.i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
+                 .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
+                 .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), 
.i7(rd_eop_o[7]),.o(rd3_eop_o));
+   
    mux8 #(.WIDTH(32))
      mux8_rd_dat_3 (.en(~read_src[3][3]),.sel(read_src[3][2:0]), 
.i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
                    .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
                    .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), 
.i7(rd_dat_o[7]),.o(rd3_dat_o));
-
+   
    assign sys_int_o = (|error) | (|done);
    //assign sys_int_o = 0;
-      
+   
 endmodule // buffer_pool
-