[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 10/42] tcg/riscv: Add the relocation functions
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 10/42] tcg/riscv: Add the relocation functions |
Date: |
Wed, 26 Dec 2018 07:54:57 +1100 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 88 ++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index d198cfd5f7..a26744052f 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -422,3 +422,91 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
}
}
+
+/*
+ * Relocations
+ */
+
+static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+
+ if (offset == sextreg(offset, 1, 12) << 1) {
+ code_ptr[0] |= encode_sbimm12(offset);
+ return true;
+ }
+
+ return false;
+}
+
+static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+
+ if (offset == sextreg(offset, 1, 20) << 1) {
+ code_ptr[0] |= encode_ujimm20(offset);
+ return true;
+ }
+
+ return false;
+}
+
+static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+ int32_t lo = sextreg(offset, 0, 12);
+ int32_t hi = offset - lo;
+
+ if (offset == hi + lo) {
+ code_ptr[0] |= encode_uimm20(hi);
+ code_ptr[1] |= encode_imm12(lo);
+ return true;
+ }
+
+ return false;
+}
+
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ uint32_t insn = *code_ptr;
+ intptr_t diff;
+ bool short_jmp;
+
+ tcg_debug_assert(addend == 0);
+
+ switch (type) {
+ case R_RISCV_BRANCH:
+ diff = value - (uintptr_t)code_ptr;
+ short_jmp = diff == sextreg(diff, 0, 12);
+ if (short_jmp) {
+ return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value);
+ } else {
+ /* Invert the condition */
+ insn = insn ^ (1 << 12);
+ /* Clear the offset */
+ insn &= 0x01fff07f;
+ /* Set the offset to the PC + 8 */
+ insn |= encode_sbimm12(8);
+
+ /* Move forward */
+ code_ptr[0] = insn;
+
+ /* Overwrite the NOP with jal x0,value */
+ diff = value - (uintptr_t)(code_ptr + 1);
+ insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff);
+ code_ptr[1] = insn;
+
+ return true;
+ }
+ break;
+ case R_RISCV_JAL:
+ return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
+ break;
+ case R_RISCV_CALL:
+ return reloc_call(code_ptr, (tcg_insn_unit *)value);
+ break;
+ default:
+ tcg_abort();
+ }
+}
--
2.17.2
- [Qemu-devel] [PULL 00/42] tcg queued patches, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 01/42] elf.h: Add the RISCV ELF magic numbers, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 02/42] linux-user: Add host dependency for RISC-V 32-bit, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 03/42] linux-user: Add host dependency for RISC-V 64-bit, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 04/42] exec: Add RISC-V GCC poison macro, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 05/42] tcg/riscv: Add the tcg-target.h file, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 06/42] tcg/riscv: Add the tcg target registers, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 07/42] tcg/riscv: Add support for the constraints, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 08/42] tcg/riscv: Add the immediate encoders, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 09/42] tcg/riscv: Add the instruction emitters, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 10/42] tcg/riscv: Add the relocation functions,
Richard Henderson <=
- [Qemu-devel] [PULL 11/42] tcg/riscv: Add the mov and movi instruction, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 12/42] tcg/riscv: Add the extract instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 14/42] tcg/riscv: Add the add2 and sub2 instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 13/42] tcg/riscv: Add the out load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 15/42] tcg/riscv: Add branch and jump instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 16/42] tcg/riscv: Add slowpath load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 17/42] tcg/riscv: Add direct load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 18/42] tcg/riscv: Add the out op decoder, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 20/42] tcg/riscv: Add the target init code, Richard Henderson, 2018/12/25