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[Qemu-devel] [PULL 09/42] tcg/riscv: Add the instruction emitters
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 09/42] tcg/riscv: Add the instruction emitters |
Date: |
Wed, 26 Dec 2018 07:54:56 +1100 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 48 ++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 08838027cd..d198cfd5f7 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -374,3 +374,51 @@ static int32_t encode_uj(RISCVInsn opc, TCGReg rd,
uint32_t imm)
{
return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
}
+
+/*
+ * RISC-V instruction emitters
+ */
+
+static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, TCGReg rs1, TCGReg rs2)
+{
+ tcg_out32(s, encode_r(opc, rd, rs1, rs2));
+}
+
+static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, TCGReg rs1, TCGArg imm)
+{
+ tcg_out32(s, encode_i(opc, rd, rs1, imm));
+}
+
+static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
+ TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ tcg_out32(s, encode_s(opc, rs1, rs2, imm));
+}
+
+static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
+ TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
+}
+
+static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, uint32_t imm)
+{
+ tcg_out32(s, encode_u(opc, rd, imm));
+}
+
+static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, uint32_t imm)
+{
+ tcg_out32(s, encode_uj(opc, rd, imm));
+}
+
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ int i;
+ for (i = 0; i < count; ++i) {
+ p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
+ }
+}
--
2.17.2
- [Qemu-devel] [PULL 00/42] tcg queued patches, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 01/42] elf.h: Add the RISCV ELF magic numbers, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 02/42] linux-user: Add host dependency for RISC-V 32-bit, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 03/42] linux-user: Add host dependency for RISC-V 64-bit, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 04/42] exec: Add RISC-V GCC poison macro, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 05/42] tcg/riscv: Add the tcg-target.h file, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 06/42] tcg/riscv: Add the tcg target registers, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 07/42] tcg/riscv: Add support for the constraints, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 08/42] tcg/riscv: Add the immediate encoders, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 09/42] tcg/riscv: Add the instruction emitters,
Richard Henderson <=
- [Qemu-devel] [PULL 10/42] tcg/riscv: Add the relocation functions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 11/42] tcg/riscv: Add the mov and movi instruction, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 12/42] tcg/riscv: Add the extract instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 14/42] tcg/riscv: Add the add2 and sub2 instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 13/42] tcg/riscv: Add the out load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 15/42] tcg/riscv: Add branch and jump instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 16/42] tcg/riscv: Add slowpath load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 17/42] tcg/riscv: Add direct load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 18/42] tcg/riscv: Add the out op decoder, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT, Richard Henderson, 2018/12/25