Re: [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen

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Re: [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with t

From:	Richard Henderson
Subject:	Re: [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch()
Date:	Sat, 13 Oct 2018 12:39:58 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0

On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +static bool trans_branch(DisasContext *ctx, arg_branch *a, TCGCond cond)

I think you should still call it gen_branch.
Reserve the trans_ prefix for things called from the decoder.

Otherwise,
Reviewed-by: Richard Henderson <address@hidden>


r~

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Re: [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, (continued)
- [Qemu-devel] [PATCH 24/28] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/12
  - Re: [Qemu-devel] [PATCH 24/28] target/riscv: Remove shift and slt insn manual decoding, Richard Henderson, 2018/10/13
- [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2018/10/12
  - Re: [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G(), Richard Henderson, 2018/10/13
- [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store(), Bastian Koppelmann, 2018/10/12
  - Re: [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store(), Richard Henderson, 2018/10/13
- [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2018/10/12
  - Re: [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn, Richard Henderson, 2018/10/13
- [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch(), Bastian Koppelmann, 2018/10/12
  - Re: [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch(), Richard Henderson <=
- [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/12
  - Re: [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Richard Henderson, 2018/10/13
- [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false, Bastian Koppelmann, 2018/10/12
  - Re: [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false, Richard Henderson, 2018/10/13
- [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/12
  - Re: [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D insns to decodetree, Richard Henderson, 2018/10/13
- [Qemu-devel] [PATCH 12/28] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2018/10/12
  - Re: [Qemu-devel] [PATCH 12/28] target/riscv: Convert RV32D insns to decodetree, Richard Henderson, 2018/10/13
- [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load(), Bastian Koppelmann, 2018/10/12
  - Re: [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load(), Richard Henderson, 2018/10/13

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