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Re: [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with tra
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load() |
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Date: |
Sat, 13 Oct 2018 12:44:13 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +static bool trans_load(DisasContext *ctx, arg_lb *a, int memop)
Again, gen_load.
> {
> - gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + if (memop < 0) {
> + return false;
> + }
This can't happen anymore.
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch(), (continued)
- [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 12/28] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load(), Bastian Koppelmann, 2018/10/12
- Re: [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load(),
Richard Henderson <=
- [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/12