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[Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G()
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G() |
Date: |
Fri, 12 Oct 2018 19:30:46 +0200 |
decodetree handles all instructions now so the fallback is not necessary
anymore.
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/translate.c | 23 -----------------------
1 file changed, 23 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 86ca885c7e..8ef943f6c8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -412,27 +412,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
-static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
-{
- int rs1, rd;
- uint32_t op;
-
- /* We do not do misaligned address check here: the address should never be
- * misaligned at this point. Instructions that set PC must do the check,
- * since epc must be the address of the instruction that caused us to
- * perform the misaligned instruction fetch */
-
- op = MASK_OP_MAJOR(ctx->opcode);
- rs1 = GET_RS1(ctx->opcode);
- rd = GET_RD(ctx->opcode);
-
- switch (op) {
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
static void decode_opc(CPURISCVState *env, DisasContext *ctx)
{
/* check for compressed insn */
@@ -448,8 +427,6 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, ctx->opcode)) {
- /* fallback to old decoder */
- decode_RV32_64G(env, ctx);
}
}
}
--
2.19.1
- [Qemu-devel] [PATCH 17/28] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, (continued)
- [Qemu-devel] [PATCH 17/28] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 09/28] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 26/28] target/riscv: Remove gen_system(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 24/28] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G(),
Bastian Koppelmann <=
- [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false, Bastian Koppelmann, 2018/10/12