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[Stable-7.2.15 23/33] target/riscv/csr.c: Fix an access to VXSAT
From: |
Michael Tokarev |
Subject: |
[Stable-7.2.15 23/33] target/riscv/csr.c: Fix an access to VXSAT |
Date: |
Sat, 9 Nov 2024 09:38:49 +0300 |
From: Evgenii Prokopiev <evgenii.prokopiev@syntacore.com>
The register VXSAT should be RW only to the first bit.
The remaining bits should be 0.
The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture
The vxsat CSR has a single read-write least-significant bit (vxsat[0])
that indicates if a fixed-point instruction has had to saturate an output
value to fit into a destination format. Bits vxsat[XLEN-1:1]
should be written as zeros.
Signed-off-by: Evgenii Prokopiev <evgenii.prokopiev@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241002084436.89347-1-evgenii.prokopiev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit 5a60026cad4e9dba929cab4f63229e4b9110cf0a)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 15dba5f653..7a3bc7bea6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -494,7 +494,7 @@ static RISCVException write_vxrm(CPURISCVState *env, int
csrno,
static RISCVException read_vxsat(CPURISCVState *env, int csrno,
target_ulong *val)
{
- *val = env->vxsat;
+ *val = env->vxsat & BIT(0);
return RISCV_EXCP_NONE;
}
@@ -504,7 +504,7 @@ static RISCVException write_vxsat(CPURISCVState *env, int
csrno,
#if !defined(CONFIG_USER_ONLY)
env->mstatus |= MSTATUS_VS;
#endif
- env->vxsat = val;
+ env->vxsat = val & BIT(0);
return RISCV_EXCP_NONE;
}
--
2.39.5
- [Stable-7.2.15 17/33] target/i386: Walk NPT in guest real mode, (continued)
- [Stable-7.2.15 17/33] target/i386: Walk NPT in guest real mode, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 18/33] linux-user/ppc: Fix sigmask endianness issue in sigreturn, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 21/33] net/tap-win32: Fix gcc 14 format truncation errors, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 19/33] gitlab: make check-[dco|patch] a little more verbose, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 20/33] Fix calculation of minimum in colo_compare_tcp, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 25/33] hw/intc: Don't clear pending bits on IRQ lowering, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 22/33] target/arm: Don't assert in regime_is_user() for E10 mmuidx values, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 26/33] target/riscv: Set vtype.vill on CPU reset, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 23/33] target/riscv/csr.c: Fix an access to VXSAT,
Michael Tokarev <=
- [Stable-7.2.15 29/33] target/riscv: Fix vcompress with rvv_ta_all_1s, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 24/33] target/riscv: Correct SXL return value for RV32 in RV64 QEMU, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 28/33] hw/intc/riscv_aplic: Check and update pending when write sourcecfg, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 30/33] target/ppc: Set ctx->opcode for decode_insn32(), Michael Tokarev, 2024/11/09
- [Stable-7.2.15 32/33] hw/nvme: fix handling of over-committed queues, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 27/33] hw/intc/riscv_aplic: Fix in_clrip[x] read emulation, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 33/33] 9pfs: fix crash on 'Treaddir' request, Michael Tokarev, 2024/11/09
- [Stable-7.2.15 31/33] target/arm: Fix SVE SDOT/UDOT/USDOT (4-way, indexed), Michael Tokarev, 2024/11/09
- Re: [Stable-7.2.15 v1 00/33] Patch Round-up for stable 7.2.15, freeze on 2024-11-18, Paolo Bonzini, 2024/11/09