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[Stable-9.0.1 53/71] target/riscv/kvm: Fix exposure of Zkr
From: |
Michael Tokarev |
Subject: |
[Stable-9.0.1 53/71] target/riscv/kvm: Fix exposure of Zkr |
Date: |
Fri, 7 Jun 2024 22:13:34 +0300 |
From: Andrew Jones <ajones@ventanamicro.com>
The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.
Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.
Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit 86997772fa807f3961e5aeed97af7738adec1b43)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3b1a02b944..52fb8c15d0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -821,6 +821,9 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations
*ops);
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+ target_ulong write_mask);
+
uint8_t satp_mode_max_from_map(uint32_t map);
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 726096444f..829d8346ed 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -4267,10 +4267,8 @@ static RISCVException write_upmbase(CPURISCVState *env,
int csrno,
#endif
/* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
- target_ulong *ret_value,
- target_ulong new_value,
- target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+ target_ulong write_mask)
{
uint16_t random_v;
Error *random_e = NULL;
@@ -4294,6 +4292,18 @@ static RISCVException rmw_seed(CPURISCVState *env, int
csrno,
rval = random_v | SEED_OPST_ES16;
}
+ return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+ target_ulong *ret_value,
+ target_ulong new_value,
+ target_ulong write_mask)
+{
+ target_ulong rval;
+
+ rval = riscv_new_csr_seed(new_value, write_mask);
+
if (ret_value) {
*ret_value = rval;
}
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index ee69ea9785..243a624fee 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1418,6 +1418,28 @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct
kvm_run *run)
return ret;
}
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+ target_ulong csr_num = run->riscv_csr.csr_num;
+ target_ulong new_value = run->riscv_csr.new_value;
+ target_ulong write_mask = run->riscv_csr.write_mask;
+ int ret = 0;
+
+ switch (csr_num) {
+ case CSR_SEED:
+ run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: un-handled CSR EXIT for CSR %lx\n",
+ __func__, csr_num);
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
{
int ret = 0;
@@ -1425,6 +1447,9 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run
*run)
case KVM_EXIT_RISCV_SBI:
ret = kvm_riscv_handle_sbi(cs, run);
break;
+ case KVM_EXIT_RISCV_CSR:
+ ret = kvm_riscv_handle_csr(cs, run);
+ break;
default:
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
__func__, run->exit_reason);
--
2.39.2
- [Stable-9.0.1 00/71] Patch Round-up for stable 9.0.1, frozen on 2024-06-07, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 45/71] gitlab: use $MAKE instead of 'make', Michael Tokarev, 2024/06/07
- [Stable-9.0.1 46/71] gitlab: use 'setarch -R' to workaround tsan bug, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 47/71] hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registers, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 48/71] hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n>, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 49/71] target/arm: Disable SVE extensions when SVE is disabled, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 50/71] qio: Inherit follow_coroutine_ctx across TLS, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 51/71] iotests: test NBD+TLS+iothread, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 52/71] hw/intc/riscv_aplic: APLICs should add child earlier than realize, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 53/71] target/riscv/kvm: Fix exposure of Zkr,
Michael Tokarev <=
- [Stable-9.0.1 54/71] target/riscv/kvm: tolerate KVM disable ext errors, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 55/71] target/riscv: Fix the element agnostic function problem, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 56/71] target/riscv/cpu.c: fix Zvkb extension config, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 57/71] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 58/71] target/riscv: rvv: Check single width operator for vector fp widen instructions, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 59/71] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 60/71] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 61/71] target/riscv: prioritize pmp errors in raise_mmu_exception(), Michael Tokarev, 2024/06/07
- [Stable-9.0.1 62/71] target/riscv: do not set mtval2 for non guest-page faults, Michael Tokarev, 2024/06/07
- [Stable-9.0.1 63/71] target/riscv: rvzicbo: Fixup CBO extension register calculation, Michael Tokarev, 2024/06/07