Re: [PATCH 2/4] tests/tcg/s390x: Test CLC with inaccessible second operand

[Ilya Leoshkevich]

On Tue, 2023-10-31 at 15:53 -0700, Richard Henderson wrote:
> On 10/30/23 22:32, Ilya Leoshkevich wrote:
> > +int main(void)
> > +{
> > +    register unsigned long r0 asm("r0");
> > +    unsigned long mem = 42, rhs = 500;
> > +    struct sigaction act;
> > +    int err;
> > +
> > +    memset(&act, 0, sizeof(act));
> > +    act.sa_sigaction = handle_sigsegv;
> > +    act.sa_flags = SA_SIGINFO;
> > +    err = sigaction(SIGSEGV, &act, NULL);
> > +    assert(err == 0);
> > +
> > +    r0 = 100;
> > +    asm("algr %[r0],%[rhs]\n"
> > +        "clc 0(8,%[mem]),0(0)\n"  /* The 2nd operand will cause a
> > SEGV. */
> > +        : [r0] "+r" (r0)
> > +        : [mem] "r" (&mem)
> > +        , [rhs] "r" (rhs)
> > +        : "cc", "memory");
> > +
> 
> You could just as easily set cc based on CHI or something to avoid
> hard-coding r0, or even 
> clobbering an output register at all.

The point of hardcoding r0 is rather to be able to check its value in
handle_sigsegv(). While this was not buggy, I still wanted to make sure
that the updated value is "committed" despite SEGV.

> 
> But I guess there's little point bike shedding this too much...
> 
> r~