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[PATCH v1 14/20] s390x/tcg: Implement 32/128 bit for VECTOR FP SQUARE RO
From: |
David Hildenbrand |
Subject: |
[PATCH v1 14/20] s390x/tcg: Implement 32/128 bit for VECTOR FP SQUARE ROOT |
Date: |
Wed, 30 Sep 2020 16:55:17 +0200 |
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 3 +++
target/s390x/translate_vx.c.inc | 26 +++++++++++++++++++++-----
target/s390x/vec_fpu_helper.c | 28 +++++++++++++++-------------
3 files changed, 39 insertions(+), 18 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 79e3fa14f8..bee283e3d4 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -321,8 +321,11 @@ DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr,
cptr, cptr, cptr, env
DEF_HELPER_FLAGS_6(gvec_vfma64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
DEF_HELPER_FLAGS_6(gvec_vfms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
+DEF_HELPER_FLAGS_4(gvec_vfsq32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vfsq32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfsq64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfsq64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vfsq128, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfs32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfs32s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env,
i32)
DEF_HELPER_FLAGS_5(gvec_vfs64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
index ee79d97e19..7d4811ccf7 100644
--- a/target/s390x/translate_vx.c.inc
+++ b/target/s390x/translate_vx.c.inc
@@ -2955,16 +2955,32 @@ static DisasJumpType op_vfsq(DisasContext *s, DisasOps
*o)
{
const uint8_t fpf = get_field(s, m3);
const uint8_t m4 = get_field(s, m4);
- gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfsq64;
+ const bool se = extract32(m4, 3, 1);
+ gen_helper_gvec_2_ptr *fn = NULL;
- if (fpf != FPF_LONG || extract32(m4, 0, 3)) {
+ switch (fpf) {
+ case FPF_SHORT:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
+ fn = se ? gen_helper_gvec_vfsq32s : gen_helper_gvec_vfsq32;
+ }
+ break;
+ case FPF_LONG:
+ fn = se ? gen_helper_gvec_vfsq64s : gen_helper_gvec_vfsq64;
+ break;
+ case FPF_EXT:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
+ fn = gen_helper_gvec_vfsq128;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (!fn || extract32(m4, 0, 3)) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- if (extract32(m4, 3, 1)) {
- fn = gen_helper_gvec_vfsq64s;
- }
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
0, fn);
return DISAS_NEXT;
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index f8ebd04516..b7045e85d6 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -744,22 +744,24 @@ void HELPER(gvec_vfms64s)(void *v1, const void *v2, const
void *v3,
vfma64(v1, v2, v3, v4, env, true, float_muladd_negate_c, GETPC());
}
-static uint64_t vfsq64(uint64_t a, float_status *s)
-{
- return float64_sqrt(a, s);
-}
-
-void HELPER(gvec_vfsq64)(void *v1, const void *v2, CPUS390XState *env,
- uint32_t desc)
-{
- vop64_2(v1, v2, env, false, false, 0, vfsq64, GETPC());
+#define DEF_GVEC_VFSQ(BITS)
\
+void HELPER(gvec_vfsq##BITS)(void *v1, const void *v2, CPUS390XState *env,
\
+ uint32_t desc)
\
+{
\
+ vop##BITS##_2(v1, v2, env, false, false, 0, float##BITS##_sqrt, GETPC());
\
}
+DEF_GVEC_VFSQ(32)
+DEF_GVEC_VFSQ(64)
+DEF_GVEC_VFSQ(128)
-void HELPER(gvec_vfsq64s)(void *v1, const void *v2, CPUS390XState *env,
- uint32_t desc)
-{
- vop64_2(v1, v2, env, true, false, 0, vfsq64, GETPC());
+#define DEF_GVEC_VFSQ_S(BITS)
\
+void HELPER(gvec_vfsq##BITS##s)(void *v1, const void *v2, CPUS390XState *env,
\
+ uint32_t desc)
\
+{
\
+ vop##BITS##_2(v1, v2, env, true, false, 0, float##BITS##_sqrt, GETPC());
\
}
+DEF_GVEC_VFSQ_S(32)
+DEF_GVEC_VFSQ_S(64)
#define DEF_GVEC_FVS(BITS)
\
void HELPER(gvec_vfs##BITS)(void *v1, const void *v2, const void *v3,
\
--
2.26.2
- [PATCH v1 02/20] s390x/tcg: Implement VECTOR BIT PERMUTE, (continued)
- [PATCH v1 02/20] s390x/tcg: Implement VECTOR BIT PERMUTE, David Hildenbrand, 2020/09/30
- [PATCH v1 04/20] s390x/tcg: Implement 32/128 bit for VECTOR FP ADD, David Hildenbrand, 2020/09/30
- [PATCH v1 06/20] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY, David Hildenbrand, 2020/09/30
- [PATCH v1 08/20] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR, David Hildenbrand, 2020/09/30
- [PATCH v1 07/20] s390x/tcg: Implement 32/128 bit for VECTOR FP SUBTRACT, David Hildenbrand, 2020/09/30
- [PATCH v1 10/20] s390x/tcg: Implement 32/128 bit for VECTOR LOAD FP INTEGER, David Hildenbrand, 2020/09/30
- [PATCH v1 09/20] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *, David Hildenbrand, 2020/09/30
- [PATCH v1 11/20] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED, David Hildenbrand, 2020/09/30
- [PATCH v1 12/20] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED, David Hildenbrand, 2020/09/30
- [PATCH v1 13/20] s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION, David Hildenbrand, 2020/09/30
- [PATCH v1 14/20] s390x/tcg: Implement 32/128 bit for VECTOR FP SQUARE ROOT,
David Hildenbrand <=
- [PATCH v1 16/20] s390x/tcg: Implement 32/128bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT), David Hildenbrand, 2020/09/30
- [PATCH v1 15/20] s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE, David Hildenbrand, 2020/09/30
- [PATCH v1 17/20] s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT), David Hildenbrand, 2020/09/30
- [PATCH v1 18/20] s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM), David Hildenbrand, 2020/09/30
- [PATCH v1 19/20] s390x/tcg: We support Vector enhancements facility, David Hildenbrand, 2020/09/30
- [PATCH v1 20/20] s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2, David Hildenbrand, 2020/09/30
- Re: [PATCH v1 00/20] s390x/tcg: Implement Vector enhancements facility and switch to z14, no-reply, 2020/09/30