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[qemu-s390x] [PULL 3/7] s390x/mmu: ASC selection in s390_cpu_get_phys_pa
From: |
Cornelia Huck |
Subject: |
[qemu-s390x] [PULL 3/7] s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug() |
Date: |
Thu, 22 Aug 2019 15:58:35 +0200 |
From: David Hildenbrand <address@hidden>
Let's select the ASC before calling the function. This is a prepararion
to remove the ASC magic depending on the access mode from mmu_translate.
There is currently no way to distinguish if we have code or data access.
For now, we were using code access, because especially when debugging with
the gdbstub, we want to read and disassemble what we single-step.
Note: KVM guest can now no longer be crashed using qmp/hmp/gdbstub if they
happen to be in AR mode.
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Cornelia Huck <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
---
target/s390x/helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index 1350ad319aba..948c0398d461 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -58,6 +58,11 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr
vaddr)
vaddr &= 0x7fffffff;
}
+ /* We want to read the code (e.g., see what we are single-stepping).*/
+ if (asc != PSW_ASC_HOME) {
+ asc = PSW_ASC_PRIMARY;
+ }
+
if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) {
return -1;
}
--
2.20.1
- [qemu-s390x] [PULL 0/7] First batch of s390x changes for 4.2, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PATCH for-4.1?] compat: disable edid on virtio-gpu base device, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 1/7] s390x/tcg: Fix VERIM with 32/64 bit elements, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 2/7] s390x/mmu: Trace the right value if setting/getting the storage key fails, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 3/7] s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug(),
Cornelia Huck <=
- [qemu-s390x] [PULL 4/7] s390x/tcg: Rework MMU selection for instruction fetches, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 5/7] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 6/7] s390x/mmu: Better storage key reference and change bit handling, Cornelia Huck, 2019/08/22
- [qemu-s390x] [PULL 7/7] s390x/mmu: Factor out storage key handling, Cornelia Huck, 2019/08/22
- Re: [qemu-s390x] [PULL 0/7] First batch of s390x changes for 4.2, Peter Maydell, 2019/08/23