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Re: [qemu-s390x] [PATCH-for-4.2 v1 2/6] s390x/tcg: Rework MMU selection
From: |
David Hildenbrand |
Subject: |
Re: [qemu-s390x] [PATCH-for-4.2 v1 2/6] s390x/tcg: Rework MMU selection for instruction fetches |
Date: |
Tue, 13 Aug 2019 14:53:23 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 |
On 13.08.19 14:52, Cornelia Huck wrote:
> On Mon, 12 Aug 2019 15:37:39 +0200
> David Hildenbrand <address@hidden> wrote:
>
>> On 12.08.19 13:27, David Hildenbrand wrote:
>>> Instructions are always fetched from primary address space, except when
>>> in home address mode. Perform the selection directly in cpu_mmu_index().
>>>
>>> get_mem_index() is only used to perform data access, instructions are
>>> fetched via cpu_lduw_code(), which translates to cpu_mmu_index(env, true).
>>>
>>> We don't care about restricting the access permissions of the TLB
>>> entries anymore, as we no longer enter PRIMARY entries into the
>>> SECONDARY MMU. Cleanup related code a bit.
>>>
>>> Signed-off-by: David Hildenbrand <address@hidden>
>>> ---
>>> target/s390x/cpu.h | 7 +++++++
>>> target/s390x/mmu_helper.c | 35 ++++++++++++++---------------------
>>> 2 files changed, 21 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
>>> index a606547b4d..c34992bb2e 100644
>>> --- a/target/s390x/cpu.h
>>> +++ b/target/s390x/cpu.h
>>> @@ -332,6 +332,13 @@ static inline int cpu_mmu_index(CPUS390XState *env,
>>> bool ifetch)
>>> return MMU_REAL_IDX;
>>> }
>>>
>>> + if (ifetch) {
>>> + if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
>>> + return MMU_HOME_IDX;
>>> + }
>>> + return MMU_PRIMARY_IDX;
>>> + }
>>> +
>>> switch (env->psw.mask & PSW_MASK_ASC) {
>>> case PSW_ASC_PRIMARY:
>>> return MMU_PRIMARY_IDX;
>>> diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
>>> index 6e9c4d6151..2c9bb3acc0 100644
>>> --- a/target/s390x/mmu_helper.c
>>> +++ b/target/s390x/mmu_helper.c
>>> @@ -349,6 +349,7 @@ int mmu_translate(CPUS390XState *env, target_ulong
>>> vaddr, int rw, uint64_t asc,
>>> {
>>> static S390SKeysState *ss;
>>> static S390SKeysClass *skeyclass;
>>> + uint64_t asce;
>>> int r = -1;
>>
>> I can now stop initializing r.
>>
>>> uint8_t key;
>>>
>>> @@ -381,35 +382,21 @@ int mmu_translate(CPUS390XState *env, target_ulong
>>> vaddr, int rw, uint64_t asc,
>>> if (!(env->psw.mask & PSW_MASK_DAT)) {
>>> *raddr = vaddr;
>>> r = 0;
>>
>> and this can go as well.
>>
>>> - goto out;
>>> + goto nodat;
>>> }
>>>
>>
>>
>
> So, there will be a v2?
Yes, but waiting for more feedback.
--
Thanks,
David / dhildenb
[qemu-s390x] [PATCH-for-4.2 v1 2/6] s390x/tcg: Rework MMU selection for instruction fetches, David Hildenbrand, 2019/08/12
Re: [qemu-s390x] [PATCH-for-4.2 v1 2/6] s390x/tcg: Rework MMU selection for instruction fetches, Cornelia Huck, 2019/08/13
[qemu-s390x] [PATCH-for-4.2 v1 3/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE, David Hildenbrand, 2019/08/12
[qemu-s390x] [PATCH-for-4.2 v1 4/6] s390x/mmu: Trace the right value if setting/getting the storage key fails, David Hildenbrand, 2019/08/12
[qemu-s390x] [PATCH-for-4.2 v1 5/6] s390x/mmu: Better storage key reference and change bit handling, David Hildenbrand, 2019/08/12
[qemu-s390x] [PATCH-for-4.2 v1 6/6] s390x/mmu: Factor out storage key handling, David Hildenbrand, 2019/08/12