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[qemu-s390x] [PULL 28/46] s390x/pci: search for subregion inside the BAR
From: |
Cornelia Huck |
Subject: |
[qemu-s390x] [PULL 28/46] s390x/pci: search for subregion inside the BARs |
Date: |
Thu, 14 Dec 2017 18:09:46 +0100 |
From: Pierre Morel <address@hidden>
When dispatching memory access to PCI BAR region, we must
look for possible subregions, used by the PCI device to map
different memory areas inside the same PCI BAR.
Since the data offset we received is calculated starting at the
region start address we need to adjust the offset for the subregion.
The data offset inside the subregion is calculated by substracting
the subregion's starting address from the data offset in the region.
The access to the MSIX region is now handled in a generic way,
we do not need the specific trap_msix() function anymore.
Signed-off-by: Pierre Morel <address@hidden>
Reviewed-by: Yi Min Zhao <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
---
hw/s390x/s390-pci-inst.c | 44 +++++++++++++++++++++++++-------------------
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 4b3be7af83..be449210d9 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -349,12 +349,31 @@ static int zpci_endian_swap(uint64_t *ptr, uint8_t len)
return 0;
}
+static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset,
+ uint8_t len)
+{
+ MemoryRegion *subregion;
+ uint64_t subregion_size;
+
+ QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
+ subregion_size = int128_get64(subregion->size);
+ if ((offset >= subregion->addr) &&
+ (offset + len) <= (subregion->addr + subregion_size)) {
+ mr = subregion;
+ break;
+ }
+ }
+ return mr;
+}
+
static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
uint64_t offset, uint64_t *data, uint8_t len)
{
MemoryRegion *mr;
mr = pbdev->pdev->io_regions[pcias].memory;
+ mr = s390_get_subregion(mr, offset, len);
+ offset -= mr->addr;
return memory_region_dispatch_read(mr, offset, data, len,
MEMTXATTRS_UNSPECIFIED);
}
@@ -446,30 +465,14 @@ int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t
r2, uintptr_t ra)
return 0;
}
-static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias)
-{
- if (pbdev->msix.available && pbdev->msix.table_bar == pcias &&
- offset >= pbdev->msix.table_offset &&
- offset < (pbdev->msix.table_offset +
- pbdev->msix.entries * PCI_MSIX_ENTRY_SIZE)) {
- return 1;
- } else {
- return 0;
- }
-}
-
static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
uint64_t offset, uint64_t data, uint8_t len)
{
MemoryRegion *mr;
- if (trap_msix(pbdev, offset, pcias)) {
- offset = offset - pbdev->msix.table_offset;
- mr = &pbdev->pdev->msix_table_mmio;
- } else {
- mr = pbdev->pdev->io_regions[pcias].memory;
- }
-
+ mr = pbdev->pdev->io_regions[pcias].memory;
+ mr = s390_get_subregion(mr, offset, len);
+ offset -= mr->addr;
return memory_region_dispatch_write(mr, offset, data, len,
MEMTXATTRS_UNSPECIFIED);
}
@@ -733,6 +736,9 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t
r3, uint64_t gaddr,
}
mr = pbdev->pdev->io_regions[pcias].memory;
+ mr = s390_get_subregion(mr, offset, len);
+ offset -= mr->addr;
+
if (!memory_region_access_valid(mr, offset, len, true)) {
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
return 0;
--
2.13.6
- [qemu-s390x] [PULL 18/46] s390x/tcg: use s390_program_interrupt() in SACF, (continued)
- [qemu-s390x] [PULL 18/46] s390x/tcg: use s390_program_interrupt() in SACF, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 19/46] s390x/tcg: use s390_program_interrupt() in STSI, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 20/46] s390x/tcg: drop program_interrupt(), Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 21/46] s390x/tcg: drop potential_page_fault(), Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 22/46] s390x/pci: factor out endianess conversion, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 23/46] s390x/pci: rework PCI STORE, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 24/46] s390x/pci: rework PCI LOAD, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 25/46] s390x/pci: rework PCI STORE BLOCK, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 26/46] s390x/pci: move the memory region read from pcilg, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 27/46] s390x/pci: move the memory region write from pcistg, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 28/46] s390x/pci: search for subregion inside the BARs,
Cornelia Huck <=
- [qemu-s390x] [PULL 29/46] s390x/css: unrestrict cssids, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 30/46] s390x: deprecate s390-squash-mcss machine prop, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 31/46] s390x/css: attach css bridge, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 32/46] s390x/kvm: factor out build_channel_report_mcic() into cpu.h, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 33/46] s390x/tcg: fix and cleanup mcck injection, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 34/46] s390x/tcg: implement SET CLOCK PROGRAMMABLE FIELD, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 35/46] s390x/tcg: indicate value of TODPR in STCKE, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 36/46] s390x/tcg: wire up STORE CHANNEL REPORT WORD, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 37/46] s390x/tcg: ASI/ASGI/ALSI/ALSGI are atomic with Interlocked-acccess facility 1, Cornelia Huck, 2017/12/14
- [qemu-s390x] [PULL 39/46] s390x/tcg: wire up SET ADDRESS LIMIT, Cornelia Huck, 2017/12/14