[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 0/8] target/riscv: Fix pointer mask related support
From: |
Weiwei Li |
Subject: |
[PATCH v4 0/8] target/riscv: Fix pointer mask related support |
Date: |
Fri, 31 Mar 2023 23:06:01 +0800 |
This patchset tries to fix some problem in current implementation for pointer
mask, and add support for pointer mask of instruction fetch.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v4
v2:
* drop some error patchs
* Add patch 2 and 3 to fix the new problems
* Add patch 4 and 5 to use PC-relative translation for pointer mask for
instruction fetch
v3:
* use target_pc temp instead of cpu_pc to store into badaddr in patch 3
* use dest_gpr instead of tcg_temp_new() for succ_pc in patch 4
* enable CF_PCREL for system mode in seperate patch 5
v4:
* Fix wrong pc_save value for conditional jump in patch 4
* Fix tcg_cflags overwrite problem to make CF_PCREL really work in new patch 5
* Fix tb mis-matched problem in new patch 6
Weiwei Li (8):
target/riscv: Fix pointer mask transformation for vector address
target/riscv: Update cur_pmmask/base when xl changes
target/riscv: Fix target address to update badaddr
target/riscv: Add support for PC-relative translation
accel/tcg: Fix overwrite problems of tcg_cflags
accel/tcg: Fix tb mis-matched problem when CF_PCREL is enabled
target/riscv: Enable PC-relative translation in system mode
target/riscv: Add pointer mask support for instruction fetch
accel/tcg/cpu-exec.c | 3 ++
accel/tcg/tcg-accel-ops.c | 2 +-
target/riscv/cpu.c | 31 +++++++----
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 20 ++++++-
target/riscv/csr.c | 11 ++--
target/riscv/insn_trans/trans_rvi.c.inc | 47 ++++++++++++----
target/riscv/translate.c | 72 ++++++++++++++++++-------
target/riscv/vector_helper.c | 2 +-
9 files changed, 145 insertions(+), 44 deletions(-)
--
2.25.1