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[PATCH v4 2/8] target/riscv: Update cur_pmmask/base when xl changes
From: |
Weiwei Li |
Subject: |
[PATCH v4 2/8] target/riscv: Update cur_pmmask/base when xl changes |
Date: |
Fri, 31 Mar 2023 23:06:03 +0800 |
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/csr.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d522efc0b6..43b9ad4500 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1277,8 +1277,15 @@ static RISCVException write_mstatus(CPURISCVState *env,
int csrno,
mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
}
env->mstatus = mstatus;
- env->xl = cpu_recompute_xl(env);
+ /*
+ * Except in debug mode, UXL/SXL can only be modified by higher
+ * privilege mode. So xl will not be changed in normal mode.
+ */
+ if (env->debugger) {
+ env->xl = cpu_recompute_xl(env);
+ riscv_cpu_update_mask(env);
+ }
return RISCV_EXCP_NONE;
}
--
2.25.1
- [PATCH v4 1/8] target/riscv: Fix pointer mask transformation for vector address, (continued)
- [PATCH v4 6/8] accel/tcg: Fix tb mis-matched problem when CF_PCREL is enabled, Weiwei Li, 2023/03/31
- [PATCH v4 8/8] target/riscv: Add pointer mask support for instruction fetch, Weiwei Li, 2023/03/31
- [PATCH v4 2/8] target/riscv: Update cur_pmmask/base when xl changes,
Weiwei Li <=
- [PATCH v4 3/8] target/riscv: Fix target address to update badaddr, Weiwei Li, 2023/03/31
- [PATCH v4 7/8] target/riscv: Enable PC-relative translation in system mode, Weiwei Li, 2023/03/31
- [PATCH v4 4/8] target/riscv: Add support for PC-relative translation, Weiwei Li, 2023/03/31