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[PATCH for-8.1 v3 22/26] target/riscv: use misa_ext val in riscv_cpu_val
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-8.1 v3 22/26] target/riscv: use misa_ext val in riscv_cpu_validate_extensions() |
Date: |
Sat, 18 Mar 2023 17:04:32 -0300 |
Similar to what we did with riscv_cpu_validate_misa_ext(), let's read
all MISA bits from a misa_ext val instead of reading from the cpu->cfg
object.
This will allow write_misa() to use riscv_cpu_validate_extensions().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 69fc0d17a5..e9172ec310 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1118,10 +1118,13 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,
Error **errp)
}
/*
- * Check consistency between chosen extensions. No changes
- * in env->misa_ext are made.
+ * Check consistency between cpu->cfg extensions and a
+ * candidate misa_ext value. No changes in env->misa_ext
+ * are made.
*/
-static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp)
+static void riscv_cpu_validate_extensions(RISCVCPU *cpu,
+ uint32_t misa_ext,
+ Error **errp)
{
if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
@@ -1132,12 +1135,12 @@ static void riscv_cpu_validate_extensions(RISCVCPU
*cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
+ if (misa_ext & RVF && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
}
- if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
+ if ((cpu->cfg.ext_zawrs) && !(misa_ext & RVA)) {
error_setg(errp, "Zawrs extension requires A extension");
return;
}
@@ -1146,13 +1149,13 @@ static void riscv_cpu_validate_extensions(RISCVCPU
*cpu, Error **errp)
cpu->cfg.ext_zfhmin = true;
}
- if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
+ if (cpu->cfg.ext_zfhmin && !(misa_ext & RVF)) {
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
return;
}
/* The V vector extension depends on the Zve64d extension */
- if (cpu->cfg.ext_v) {
+ if (misa_ext & RVV) {
cpu->cfg.ext_zve64d = true;
}
@@ -1166,12 +1169,12 @@ static void riscv_cpu_validate_extensions(RISCVCPU
*cpu, Error **errp)
cpu->cfg.ext_zve32f = true;
}
- if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
+ if (cpu->cfg.ext_zve64d && !(misa_ext & RVD)) {
error_setg(errp, "Zve64d/V extensions require D extension");
return;
}
- if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
+ if (cpu->cfg.ext_zve32f && !(misa_ext & RVF)) {
error_setg(errp, "Zve32f/Zve64f extensions require F extension");
return;
}
@@ -1204,7 +1207,7 @@ static void riscv_cpu_validate_extensions(RISCVCPU *cpu,
Error **errp)
error_setg(errp, "Zfinx extension requires Zicsr");
return;
}
- if (cpu->cfg.ext_f) {
+ if (misa_ext & RVF) {
error_setg(errp,
"Zfinx cannot be supported together with F extension");
return;
@@ -1376,7 +1379,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
- riscv_cpu_validate_extensions(cpu, &local_err);
+ riscv_cpu_validate_extensions(cpu, env->misa_ext, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
--
2.39.2
- [PATCH for-8.1 v3 13/26] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers, (continued)
- [PATCH for-8.1 v3 13/26] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers, Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 14/26] target/riscv: add RVG, Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 15/26] target/riscv/cpu.c: split RVG code from validate_set_extensions(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 16/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_ext(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 17/26] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 18/26] target/riscv: error out on priv failure for RVH, Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 19/26] target/riscv: write env->misa_ext* in register_generic_cpu_props(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 20/26] target/riscv: make validate_misa_ext() use a misa_ext val, Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 21/26] target/riscv: split riscv_cpu_validate_set_extensions(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 22/26] target/riscv: use misa_ext val in riscv_cpu_validate_extensions(),
Daniel Henrique Barboza <=
- [PATCH for-8.1 v3 23/26] target/riscv: rework write_misa(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 24/26] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 25/26] target/riscv: allow write_misa() to enable RVG, Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 26/26] target/riscv: allow write_misa() to enable RVV, Daniel Henrique Barboza, 2023/03/18