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[PATCH for-8.1 v3 15/26] target/riscv/cpu.c: split RVG code from validat
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-8.1 v3 15/26] target/riscv/cpu.c: split RVG code from validate_set_extensions() |
Date: |
Sat, 18 Mar 2023 17:04:25 -0300 |
We can set all RVG related extensions during realize time, before
validate_set_extensions() itself. Put it in a separated function so the
validate function already uses the updated state.
Note that we're adding an extra constraint: ext_zfinx is a blocker for
F, which is a requirement to enable G. If zfinx is enabled we'll have to
error out.
Note that we're setting both cfg->ext_N and env->misa_ext bits, instead
of just setting cfg->ext_N. The intention here is to start syncing all
misa_ext operations with its cpu->cfg flags, in preparation to allow for
the validate function to operate using a misa_ext. This doesn't make any
difference for the current code state, but will be a requirement for
write_misa() later on.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 66 +++++++++++++++++++++++++++++++++++-----------
1 file changed, 51 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 48ad7372b9..110b52712c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -281,6 +281,42 @@ static uint32_t
riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg)
return ext;
}
+static void riscv_cpu_enable_g(RISCVCPU *cpu, Error **errp)
+{
+ CPURISCVState *env = &cpu->env;
+ RISCVCPUConfig *cfg = &cpu->cfg;
+
+ if (cpu->cfg.ext_zfinx) {
+ error_setg(errp, "Unable to enable G: Zfinx is enabled, "
+ "so F can not be enabled");
+ return;
+ }
+
+ if (!(cfg->ext_i && cfg->ext_m && cfg->ext_a &&
+ cfg->ext_f && cfg->ext_d &&
+ cfg->ext_icsr && cfg->ext_ifencei)) {
+
+ warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
+ cfg->ext_i = true;
+ env->misa_ext |= RVI;
+
+ cfg->ext_m = true;
+ env->misa_ext |= RVM;
+
+ cfg->ext_a = true;
+ env->misa_ext |= RVA;
+
+ cfg->ext_f = true;
+ env->misa_ext |= RVF;
+
+ cfg->ext_d = true;
+ env->misa_ext |= RVD;
+
+ cfg->ext_icsr = true;
+ cfg->ext_ifencei = true;
+ }
+}
+
static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg,
uint32_t misa_ext)
{
@@ -1036,21 +1072,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
return;
}
- /* Do some ISA extension error checking */
- if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
- cpu->cfg.ext_a && cpu->cfg.ext_f &&
- cpu->cfg.ext_d &&
- cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
- warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
- cpu->cfg.ext_i = true;
- cpu->cfg.ext_m = true;
- cpu->cfg.ext_a = true;
- cpu->cfg.ext_f = true;
- cpu->cfg.ext_d = true;
- cpu->cfg.ext_icsr = true;
- cpu->cfg.ext_ifencei = true;
- }
-
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
"I and E extensions are incompatible");
@@ -1293,6 +1314,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
CPUState *cs = CPU(dev);
RISCVCPU *cpu = RISCV_CPU(dev);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
+ CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
@@ -1313,6 +1335,20 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ if (cpu->cfg.ext_g) {
+ riscv_cpu_enable_g(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ /*
+ * Sync env->misa_ext_mask with the new
+ * env->misa_ext val.
+ */
+ env->misa_ext_mask = env->misa_ext;
+ }
+
riscv_cpu_validate_set_extensions(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
--
2.39.2
- [PATCH for-8.1 v3 06/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl(), (continued)
- [PATCH for-8.1 v3 06/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 07/26] target/riscv: move pmp and epmp validations to validate_set_extensions(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 08/26] target/riscv/cpu.c: validate extensions before riscv_timer_init(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 09/26] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 10/26] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 11/26] target/riscv/cpu.c: set cpu config in set_misa(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 12/26] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 13/26] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers, Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 14/26] target/riscv: add RVG, Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 15/26] target/riscv/cpu.c: split RVG code from validate_set_extensions(),
Daniel Henrique Barboza <=
- [PATCH for-8.1 v3 16/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_ext(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 17/26] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 18/26] target/riscv: error out on priv failure for RVH, Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 19/26] target/riscv: write env->misa_ext* in register_generic_cpu_props(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 20/26] target/riscv: make validate_misa_ext() use a misa_ext val, Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 21/26] target/riscv: split riscv_cpu_validate_set_extensions(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 22/26] target/riscv: use misa_ext val in riscv_cpu_validate_extensions(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 23/26] target/riscv: rework write_misa(), Daniel Henrique Barboza, 2023/03/18
- [PATCH for-8.1 v3 24/26] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg(), Daniel Henrique Barboza, 2023/03/18