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[PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector
From: |
Palmer Dabbelt |
Subject: |
[PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml |
Date: |
Fri, 3 Mar 2023 00:37:17 -0800 |
From: Bin Meng <bmeng@tinylab.org>
It's worth noting that the vector CSR predicate() has a similar
run-time check logic to the FPU CSR. With the previous patch our
gdbstub can correctly report these vector CSRs via the CSR xml.
Commit 719d3561b269 ("target/riscv: gdb: support vector registers for rv64 &
rv32")
inserted these vector CSRs in an ad-hoc, non-standard way in the
riscv-vector.xml. Now we can treat these CSRs no different from
other CSRs.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-13-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/gdbstub.c | 75 ------------------------------------------
1 file changed, 75 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index ef52f41460..6048541606 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -127,40 +127,6 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t
*mem_buf, int n)
return 0;
}
-/*
- * Convert register index number passed by GDB to the correspond
- * vector CSR number. Vector CSRs are defined after vector registers
- * in dynamic generated riscv-vector.xml, thus the starting register index
- * of vector CSRs is 32.
- * Return 0 if register index number is out of range.
- */
-static int riscv_gdb_vector_csrno(int num_regs)
-{
- /*
- * The order of vector CSRs in the switch case
- * should match with the order defined in csr_ops[].
- */
- switch (num_regs) {
- case 32:
- return CSR_VSTART;
- case 33:
- return CSR_VXSAT;
- case 34:
- return CSR_VXRM;
- case 35:
- return CSR_VCSR;
- case 36:
- return CSR_VL;
- case 37:
- return CSR_VTYPE;
- case 38:
- return CSR_VLENB;
- default:
- /* Unknown register. */
- return 0;
- }
-}
-
static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
{
uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
@@ -174,19 +140,6 @@ static int riscv_gdb_get_vector(CPURISCVState *env,
GByteArray *buf, int n)
return cnt;
}
- int csrno = riscv_gdb_vector_csrno(n);
-
- if (!csrno) {
- return 0;
- }
-
- target_ulong val = 0;
- int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
-
- if (result == RISCV_EXCP_NONE) {
- return gdb_get_regl(buf, val);
- }
-
return 0;
}
@@ -201,19 +154,6 @@ static int riscv_gdb_set_vector(CPURISCVState *env,
uint8_t *mem_buf, int n)
return vlenb;
}
- int csrno = riscv_gdb_vector_csrno(n);
-
- if (!csrno) {
- return 0;
- }
-
- target_ulong val = ldtul_p(mem_buf);
- int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
-
- if (result == RISCV_EXCP_NONE) {
- return sizeof(target_ulong);
- }
-
return 0;
}
@@ -361,21 +301,6 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int
base_reg)
num_regs++;
}
- /* Define vector CSRs */
- const char *vector_csrs[7] = {
- "vstart", "vxsat", "vxrm", "vcsr",
- "vl", "vtype", "vlenb"
- };
-
- for (i = 0; i < 7; i++) {
- g_string_append_printf(s,
- "<reg name=\"%s\" bitsize=\"%d\""
- " regnum=\"%d\" group=\"vector\""
- " type=\"int\"/>",
- vector_csrs[i], TARGET_LONG_BITS, base_reg++);
- num_regs++;
- }
-
g_string_append_printf(s, "</feature>");
cpu->dyn_vreg_xml = g_string_free(s, false);
--
2.39.2
- [PULL 25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR, (continued)
- [PULL 25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR, Palmer Dabbelt, 2023/03/03
- [PULL 27/59] target/riscv: Use g_assert() for the predicate() NULL check, Palmer Dabbelt, 2023/03/03
- [PULL 28/59] target/riscv: gdbstub: Minor change for better readability, Palmer Dabbelt, 2023/03/03
- [PULL 29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled, Palmer Dabbelt, 2023/03/03
- [PULL 31/59] target/riscv: Use 'bool' type for read_only, Palmer Dabbelt, 2023/03/03
- [PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit, Palmer Dabbelt, 2023/03/03
- [PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env, Palmer Dabbelt, 2023/03/03
- [PULL 34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Palmer Dabbelt, 2023/03/03
- [PULL 30/59] target/riscv: Coding style fixes in csr.c, Palmer Dabbelt, 2023/03/03
- [PULL 35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml,
Palmer Dabbelt <=
- [PULL 39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages, Palmer Dabbelt, 2023/03/03
- [PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair, Palmer Dabbelt, 2023/03/03
- [PULL 38/59] target/riscv: Allow debugger to access seed CSR, Palmer Dabbelt, 2023/03/03
- [PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB, Palmer Dabbelt, 2023/03/03
- [PULL 40/59] target/riscv: Allow debugger to access sstc CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 42/59] target/riscv: Group all predicate() routines together, Palmer Dabbelt, 2023/03/03
- [PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions, Palmer Dabbelt, 2023/03/03