[PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env

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[PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env

From:	Palmer Dabbelt
Subject:	[PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env
Date:	Fri, 3 Mar 2023 00:37:14 -0800

From: Bin Meng <bmeng@tinylab.org>

Use env_archcpu() to get RISCVCPU pointer from env directly.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-10-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 target/riscv/csr.c | 36 ++++++++++++------------------------
 1 file changed, 12 insertions(+), 24 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a3e0e5755c..8e827362cc 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -46,8 +46,7 @@ static RISCVException smstateen_acc_ok(CPURISCVState *env, 
int index,
                                        uint64_t bit)
 {
     bool virt = riscv_cpu_virt_enabled(env);
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
 
     if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
         return RISCV_EXCP_NONE;
@@ -90,8 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
 
     if (env->misa_ext & RVV ||
         cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
@@ -108,8 +106,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
 static RISCVException ctr(CPURISCVState *env, int csrno)
 {
 #if !defined(CONFIG_USER_ONLY)
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
     int ctr_index;
     target_ulong ctr_mask;
     int base_csrno = CSR_CYCLE;
@@ -166,8 +163,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
 #if !defined(CONFIG_USER_ONLY)
 static RISCVException mctr(CPURISCVState *env, int csrno)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
     int ctr_index;
     int base_csrno = CSR_MHPMCOUNTER3;
 
@@ -195,8 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
 
 static RISCVException sscofpmf(CPURISCVState *env, int csrno)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
 
     if (!cpu->cfg.ext_sscofpmf) {
         return RISCV_EXCP_ILLEGAL_INST;
@@ -321,8 +316,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
 
 static RISCVException mstateen(CPURISCVState *env, int csrno)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
 
     if (!cpu->cfg.ext_smstateen) {
         return RISCV_EXCP_ILLEGAL_INST;
@@ -333,8 +327,7 @@ static RISCVException mstateen(CPURISCVState *env, int 
csrno)
 
 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
 
     if (!cpu->cfg.ext_smstateen) {
         return RISCV_EXCP_ILLEGAL_INST;
@@ -363,8 +356,7 @@ static RISCVException sstateen(CPURISCVState *env, int 
csrno)
 {
     bool virt = riscv_cpu_virt_enabled(env);
     int index = csrno - CSR_SSTATEEN0;
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
 
     if (!cpu->cfg.ext_smstateen) {
         return RISCV_EXCP_ILLEGAL_INST;
@@ -918,8 +910,7 @@ static RISCVException read_timeh(CPURISCVState *env, int 
csrno,
 
 static RISCVException sstc(CPURISCVState *env, int csrno)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
     bool hmode_check = false;
 
     if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
@@ -1152,8 +1143,7 @@ static RISCVException write_ignore(CPURISCVState *env, 
int csrno,
 static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
                                      target_ulong *val)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
 
     *val = cpu->cfg.mvendorid;
     return RISCV_EXCP_NONE;
@@ -1162,8 +1152,7 @@ static RISCVException read_mvendorid(CPURISCVState *env, 
int csrno,
 static RISCVException read_marchid(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
 
     *val = cpu->cfg.marchid;
     return RISCV_EXCP_NONE;
@@ -1172,8 +1161,7 @@ static RISCVException read_marchid(CPURISCVState *env, 
int csrno,
 static RISCVException read_mimpid(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
-    CPUState *cs = env_cpu(env);
-    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPU *cpu = env_archcpu(env);
 
     *val = cpu->cfg.mimpid;
     return RISCV_EXCP_NONE;
-- 
2.39.2

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[PULL 22/59] target/riscv: Fix check for vector load/store instructions when EEW=64, (continued)
- [PULL 22/59] target/riscv: Fix check for vector load/store instructions when EEW=64, Palmer Dabbelt, 2023/03/03
- [PULL 23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Palmer Dabbelt, 2023/03/03
- [PULL 24/59] target/riscv: Expose properties for Zv* extensions, Palmer Dabbelt, 2023/03/03
- [PULL 26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check(), Palmer Dabbelt, 2023/03/03
- [PULL 25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR, Palmer Dabbelt, 2023/03/03
- [PULL 27/59] target/riscv: Use g_assert() for the predicate() NULL check, Palmer Dabbelt, 2023/03/03
- [PULL 28/59] target/riscv: gdbstub: Minor change for better readability, Palmer Dabbelt, 2023/03/03
- [PULL 29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled, Palmer Dabbelt, 2023/03/03
- [PULL 31/59] target/riscv: Use 'bool' type for read_only, Palmer Dabbelt, 2023/03/03
- [PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit, Palmer Dabbelt, 2023/03/03
- [PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env, Palmer Dabbelt <=
- [PULL 34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Palmer Dabbelt, 2023/03/03
- [PULL 30/59] target/riscv: Coding style fixes in csr.c, Palmer Dabbelt, 2023/03/03
- [PULL 35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Palmer Dabbelt, 2023/03/03
- [PULL 39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages, Palmer Dabbelt, 2023/03/03
- [PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair, Palmer Dabbelt, 2023/03/03
- [PULL 38/59] target/riscv: Allow debugger to access seed CSR, Palmer Dabbelt, 2023/03/03
- [PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB, Palmer Dabbelt, 2023/03/03

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