Re: [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vecto

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Re: [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vecto

From:	Weiwei Li
Subject:	Re: [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
Date:	Sat, 14 May 2022 00:19:16 +0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0


在 2022/5/14 上午12:09, Weiwei Li 写道:


在 2022/3/17 下午3:47, ~eopxd 写道:

From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
  target/riscv/insn_trans/trans_rvv.c.inc |  5 ++++
  target/riscv/vector_helper.c            | 35 +++++++++++++++++--------
  2 files changed, 29 insertions(+), 11 deletions(-)


Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>

Regards,
Weiwei Li

Sorry, miss a space.

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

diff --git a/target/riscv/insn_trans/trans_rvv.c.incb/target/riscv/insn_trans/trans_rvv.c.inc

index df5a892150..a6daf20714 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc

@@ -712,6 +712,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm*a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
  }

@@ -777,6 +778,7 @@ static bool ld_us_mask_op(DisasContext *s,arg_vlm_v *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, NF, 1);
      /* Mask destination register are always tail-agnostic */
      data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
  }

@@ -866,6 +868,7 @@ static bool ld_stride_op(DisasContext *s,arg_rnfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);

return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s,false);

@@ -996,6 +999,7 @@ static bool ld_index_op(DisasContext *s,arg_rnfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);

return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s,false);

@@ -1114,6 +1118,7 @@ static bool ldff_op(DisasContext *s,arg_r2nfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldff_trans(a->rd, a->rs1, data, fn, s);
  }

diff --git a/target/riscv/vector_helper.cb/target/riscv/vector_helper.c

index 6c55d5a750..5d392d084e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c

@@ -282,14 +282,18 @@ vext_ldst_stride(void *vd, void *v0,target_ulong base,

      uint32_t esz = 1 << log2_esz;
      uint32_t total_elems = vext_get_total_elems(env, desc, esz);
      uint32_t vta = vext_vta(desc);
+    uint32_t vma = vext_vma(desc);
        for (i = env->vstart; i < env->vl; i++, env->vstart++) {
-        if (!vm && !vext_elem_mask(v0, i)) {
-            continue;
-        }
-
          k = 0;
          while (k < nf) {
+            if (!vm && !vext_elem_mask(v0, i)) {
+                /* set masked-off elements to 1s */
+                vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz,
+                                  (i + k * max_elems + 1) * esz);
+                k++;
+                continue;
+            }
              target_ulong addr = base + stride * i + (k << log2_esz);

ldst_elem(env, adjust_addr(env, addr), i + k *max_elems, vd, ra);

              k++;

@@ -481,15 +485,19 @@ vext_ldst_index(void *vd, void *v0,target_ulong base,

      uint32_t esz = 1 << log2_esz;
      uint32_t total_elems = vext_get_total_elems(env, desc, esz);
      uint32_t vta = vext_vta(desc);
+    uint32_t vma = vext_vma(desc);
        /* load bytes from guest memory */
      for (i = env->vstart; i < env->vl; i++, env->vstart++) {
-        if (!vm && !vext_elem_mask(v0, i)) {
-            continue;
-        }
-
          k = 0;
          while (k < nf) {
+            if (!vm && !vext_elem_mask(v0, i)) {
+                /* set masked-off elements to 1s */
+                vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz,
+                                  (i + k * max_elems + 1) * esz);
+                k++;
+                continue;
+            }

abi_ptr addr = get_index_addr(base, i, vs2) + (k <<log2_esz); ldst_elem(env, adjust_addr(env, addr), i + k *max_elems, vd, ra);

              k++;
@@ -578,6 +586,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
      uint32_t esz = 1 << log2_esz;
      uint32_t total_elems = vext_get_total_elems(env, desc, esz);
      uint32_t vta = vext_vta(desc);
+    uint32_t vma = vext_vma(desc);
      target_ulong addr, offset, remain;
        /* probe every access*/
@@ -623,10 +632,14 @@ ProbeSuccess:
      }
      for (i = env->vstart; i < env->vl; i++) {
          k = 0;
-        if (!vm && !vext_elem_mask(v0, i)) {
-            continue;
-        }
          while (k < nf) {
+            if (!vm && !vext_elem_mask(v0, i)) {
+                /* set masked-off elements to 1s */
+                vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz,
+                                  (i + k * max_elems + 1) * esz);
+                k++;
+                continue;
+            }
              target_ulong addr = base + ((i * nf + k) << log2_esz);

ldst_elem(env, adjust_addr(env, addr), i + k *max_elems, vd, ra);

              k++;

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[PATCH qemu v4 00/10] Add mask agnostic behavior for rvv instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions, ~eopxd, 2022/05/13
  - Re: [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions, Weiwei Li, 2022/05/13
    - Re: [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions, Weiwei Li <=
- [PATCH qemu v4 01/10] target/riscv: rvv: Add mask agnostic for vv instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 03/10] target/riscv: rvv: Add mask agnostic for vx instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, ~eopxd, 2022/05/13

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