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[PATCH qemu v4 07/10] target/riscv: rvv: Add mask agnostic for vector fl
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From: |
~eopxd |
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Subject: |
[PATCH qemu v4 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions |
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Date: |
Fri, 13 May 2022 11:58:22 -0000 |
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++++
target/riscv/vector_helper.c | 26 +++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index f87780264f..f37040f278 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2349,6 +2349,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = \
FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -2434,6 +2435,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, \
s->cfg_vta_all_1s); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2473,6 +2475,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -2513,6 +2516,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2550,6 +2554,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -2590,6 +2595,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2674,6 +2680,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env,
s->cfg_ptr->vlen / 8,
@@ -2778,6 +2785,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f
*a)
TCGv_i32 desc;
uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_vmv_vx * const fns[3] = {
gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w,
@@ -2879,6 +2887,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
@@ -2932,6 +2941,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
@@ -3000,6 +3010,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
@@ -3055,6 +3066,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 4a1d6bdde3..bcac0a9f1b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3050,10 +3050,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
uint32_t total_elems = \
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * ESZ, \
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, vs1, vs2, i, env); \
@@ -3089,10 +3093,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1,
\
uint32_t total_elems = \
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * ESZ, \
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, s1, vs2, i, env); \
@@ -3664,6 +3672,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
uint32_t total_elems = \
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
if (vl == 0) { \
@@ -3671,6 +3680,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
} \
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * ESZ, \
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, vs2, i, env); \
@@ -4181,12 +4193,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
uint32_t vl = env->vl; \
uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, \
@@ -4214,11 +4231,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void
*vs2, \
uint32_t vl = env->vl; \
uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, \
@@ -4341,10 +4363,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
uint32_t total_elems = \
vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s(vd, vma, i * ESZ, \
+ (i + 1) * ESZ); \
continue; \
} \
do_##NAME(vd, vs2, i); \
--
2.34.2
- [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions, (continued)
- [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 01/10] target/riscv: rvv: Add mask agnostic for vv instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 03/10] target/riscv: rvv: Add mask agnostic for vx instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, ~eopxd, 2022/05/13
- [PATCH qemu v4 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions,
~eopxd <=
- [PATCH qemu v4 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, ~eopxd, 2022/05/13