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Re: [PATCH qemu v14 08/15] target/riscv: rvv: Add tail agnostic for vect
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH qemu v14 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions |
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Date: |
Tue, 10 May 2022 11:33:40 +0200 |
On Tue, May 3, 2022 at 9:40 AM ~eopxd <eopxd@git.sr.ht> wrote:
>
> From: eopXD <eop.chen@sifive.com>
>
> Compares write mask registers, and so always operate under a tail-
> agnostic policy.
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/vector_helper.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index c1ae2ea2f1..ddaf364573 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -1373,6 +1373,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
> *vs2, \
> { \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
> + uint32_t vta_all_1s = vext_vta_all_1s(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> @@ -1384,6 +1386,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
> *vs2, \
> vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
> } \
> env->vstart = 0; \
> + /* mask destination register are always tail-agnostic */ \
> + /* set tail elements to 1s */ \
> + if (vta_all_1s) { \
> + for (; i < total_elems; i++) { \
> + vext_set_elem_mask(vd, i, 1); \
> + } \
> + } \
> }
>
> GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
> @@ -1422,6 +1431,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
> void *vs2, \
> { \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
> + uint32_t vta_all_1s = vext_vta_all_1s(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> @@ -1433,6 +1444,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
> void *vs2, \
> DO_OP(s2, (ETYPE)(target_long)s1)); \
> } \
> env->vstart = 0; \
> + /* mask destination register are always tail-agnostic */ \
> + /* set tail elements to 1s */ \
> + if (vta_all_1s) { \
> + for (; i < total_elems; i++) { \
> + vext_set_elem_mask(vd, i, 1); \
> + } \
> + } \
> }
>
> GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
> --
> 2.34.2
>
>
- [PATCH qemu v14 00/15] Add tail agnostic behavior for rvv instructions, ~eopxd, 2022/05/03
- [PATCH qemu v14 04/15] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/05/03
- [PATCH qemu v14 03/15] target/riscv: rvv: Early exit when vstart >= vl, ~eopxd, 2022/05/03
- [PATCH qemu v14 02/15] target/riscv: rvv: Rename ambiguous esz, ~eopxd, 2022/05/03
- [PATCH qemu v14 01/15] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/05/03
- [PATCH qemu v14 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/05/03
- Re: [PATCH qemu v14 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions,
Alistair Francis <=
- [PATCH qemu v14 05/15] target/riscv: rvv: Add tail agnostic for vector load / store instructions, ~eopxd, 2022/05/03
- [PATCH qemu v14 07/15] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, ~eopxd, 2022/05/03
- [PATCH qemu v14 06/15] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/05/03
- [PATCH qemu v14 12/15] target/riscv: rvv: Add tail agnostic for vector reduction instructions, ~eopxd, 2022/05/03
- [PATCH qemu v14 10/15] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/05/03