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[PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuratio
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From: |
frank . chang |
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Subject: |
[PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns |
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Date: |
Wed, 29 Dec 2021 10:33:39 +0800 |
From: Frank Chang <frank.chang@sifive.com>
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 230c475d6c..c6280c7b0b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -152,7 +152,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,
TCGv s2)
TCGv s1, dst;
if (!require_rvv(s) ||
- !(has_ext(s, RVV) || s->ext_zve64f)) {
+ !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
return false;
}
@@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1,
TCGv s2)
TCGv dst;
if (!require_rvv(s) ||
- !(has_ext(s, RVV) || s->ext_zve64f)) {
+ !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
return false;
}
--
2.31.1
- [PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, (continued)
- [PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, frank . chang, 2021/12/28
- [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, frank . chang, 2021/12/28
- [PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, frank . chang, 2021/12/28
- [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, frank . chang, 2021/12/28
- [PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, frank . chang, 2021/12/28
- [PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, frank . chang, 2021/12/28
- [PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, frank . chang, 2021/12/28
- [PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, frank . chang, 2021/12/28
- [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, frank . chang, 2021/12/28
- [PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, frank . chang, 2021/12/28
- [PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns,
frank . chang <=
- [PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns, frank . chang, 2021/12/28
- [PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns, frank . chang, 2021/12/28
- [PATCH 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns, frank . chang, 2021/12/28
- [PATCH 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns, frank . chang, 2021/12/28
- [PATCH 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on, frank . chang, 2021/12/28