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[PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing ty
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From: |
frank . chang |
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Subject: |
[PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns |
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Date: |
Wed, 29 Dec 2021 10:33:36 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 9ca8d502b2..230c475d6c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2824,14 +2824,16 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr
*a)
{
return opfv_narrow_check(s, a) &&
require_rvf(s) &&
- (s->sew != MO_64);
+ (s->sew != MO_64) &&
+ require_zve64f(s);
}
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
{
return opfv_narrow_check(s, a) &&
require_scale_rvf(s) &&
- (s->sew != MO_8);
+ (s->sew != MO_8) &&
+ require_scale_zve64f(s);
}
#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
@@ -2880,7 +2882,8 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr
*a)
require_scale_rvf(s) &&
vext_check_isa_ill(s) &&
/* OPFV narrowing instructions ignore vs1 check */
- vext_check_sd(s, a->rd, a->rs2, a->vm);
+ vext_check_sd(s, a->rd, a->rs2, a->vm) &&
+ require_scale_zve64f(s);
}
#define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM) \
--
2.31.1
- [PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions, frank . chang, 2021/12/28
- [PATCH 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, frank . chang, 2021/12/28
- [PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, frank . chang, 2021/12/28
- [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, frank . chang, 2021/12/28
- [PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, frank . chang, 2021/12/28
- [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, frank . chang, 2021/12/28
- [PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, frank . chang, 2021/12/28
- [PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, frank . chang, 2021/12/28
- [PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, frank . chang, 2021/12/28
- [PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns,
frank . chang <=
- [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, frank . chang, 2021/12/28
- [PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, frank . chang, 2021/12/28
- [PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns, frank . chang, 2021/12/28
- [PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns, frank . chang, 2021/12/28
- [PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns, frank . chang, 2021/12/28
- [PATCH 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns, frank . chang, 2021/12/28
- [PATCH 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns, frank . chang, 2021/12/28
- [PATCH 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on, frank . chang, 2021/12/28