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[PATCH v3 12/13] target/riscv: Return the exception from invalid CSR acc
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From: |
Alistair Francis |
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Subject: |
[PATCH v3 12/13] target/riscv: Return the exception from invalid CSR accesses |
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Date: |
Wed, 12 Aug 2020 12:13:46 -0700 |
When performing a CSR access let's return a negative exception value on
an error instead of -1. This will allow us to specify the exception in
future patches.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 46 ++++++++++++++++++++--------------------
target/riscv/op_helper.c | 18 ++++++++++------
2 files changed, 35 insertions(+), 29 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7dc50e6299..197ce97e95 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -51,7 +51,7 @@ static int fs(CPURISCVState *env, int csrno)
return 0;
}
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
return 0;
@@ -73,7 +73,7 @@ static int ctr(CPURISCVState *env, int csrno)
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
return 0;
@@ -101,7 +101,7 @@ static int hmode(CPURISCVState *env, int csrno)
}
}
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
static int pmp(CPURISCVState *env, int csrno)
@@ -115,7 +115,7 @@ static int read_fflags(CPURISCVState *env, int csrno,
target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = riscv_cpu_get_fflags(env);
@@ -126,7 +126,7 @@ static int write_fflags(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
@@ -138,7 +138,7 @@ static int read_frm(CPURISCVState *env, int csrno,
target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = env->frm;
@@ -149,7 +149,7 @@ static int write_frm(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
@@ -161,7 +161,7 @@ static int read_fcsr(CPURISCVState *env, int csrno,
target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
@@ -177,7 +177,7 @@ static int write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
@@ -291,7 +291,7 @@ static int read_time(CPURISCVState *env, int csrno,
target_ulong *val)
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->rdtime_fn() + delta;
@@ -304,7 +304,7 @@ static int read_timeh(CPURISCVState *env, int csrno,
target_ulong *val)
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = (env->rdtime_fn() + delta) >> 32;
@@ -570,7 +570,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno,
target_ulong val)
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->mcounteren;
return 0;
@@ -580,7 +580,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mcounteren = val;
return 0;
@@ -804,7 +804,7 @@ static int read_satp(CPURISCVState *env, int csrno,
target_ulong *val)
}
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
} else {
*val = env->satp;
}
@@ -821,7 +821,7 @@ static int write_satp(CPURISCVState *env, int csrno,
target_ulong val)
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
} else {
if((val ^ env->satp) & SATP_ASID) {
tlb_flush(env_cpu(env));
@@ -991,7 +991,7 @@ static int write_hgatp(CPURISCVState *env, int csrno,
target_ulong val)
static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#if defined(TARGET_RISCV32)
@@ -1005,7 +1005,7 @@ static int read_htimedelta(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#if defined(TARGET_RISCV32)
@@ -1020,7 +1020,7 @@ static int write_htimedelta(CPURISCVState *env, int
csrno, target_ulong val)
static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->htimedelta >> 32;
@@ -1030,7 +1030,7 @@ static int read_htimedeltah(CPURISCVState *env, int
csrno, target_ulong *val)
static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
@@ -1228,18 +1228,18 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
if ((write_mask && read_only) ||
(!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
/* ensure the CSR extension is enabled. */
if (!cpu->cfg.ext_icsr) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* check predicate */
if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0)
{
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* execute combined read/write operation if it exists */
@@ -1249,7 +1249,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
/* if no accessor exists then return failure */
if (!csr_ops[csrno].read) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* read old value */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 4b64bfe7d2..948d204793 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -43,8 +43,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong
src,
target_ulong csr)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, src, -1);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
@@ -53,8 +55,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong
src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
@@ -63,8 +67,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong
src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
--
2.27.0
- [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions, (continued)
- [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 03/13] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 04/13] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/08/12
- [PATCH v3 05/13] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/08/12
- [PATCH v3 06/13] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/08/12
- [PATCH v3 07/13] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/08/12
- [PATCH v3 08/13] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/08/12
- [PATCH v3 09/13] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/08/12
- [PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/08/12
- [PATCH v3 10/13] target/riscv: Only support little endian guests, Alistair Francis, 2020/08/12
- [PATCH v3 12/13] target/riscv: Return the exception from invalid CSR accesses,
Alistair Francis <=
- [PATCH v3 13/13] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/08/12
- Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1, LIU Zhiwei, 2020/08/12