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[PATCH v3 05/13] target/riscv: Convert MSTATUS MTL to GVA
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From: |
Alistair Francis |
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Subject: |
[PATCH v3 05/13] target/riscv: Convert MSTATUS MTL to GVA |
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Date: |
Wed, 12 Aug 2020 12:13:27 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 5 +++--
target/riscv/cpu_helper.c | 24 ++++++++++++++++++++----
target/riscv/csr.c | 6 +++---
3 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7abae4267f..43617e7c1f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -379,10 +379,10 @@
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
#if defined(TARGET_RISCV64)
-#define MSTATUS_MTL 0x4000000000ULL
+#define MSTATUS_GVA 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
#elif defined(TARGET_RISCV32)
-#define MSTATUS_MTL 0x00000040
+#define MSTATUS_GVA 0x00000040
#define MSTATUS_MPV 0x00000080
#endif
@@ -444,6 +444,7 @@
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_HU 0x00000200
+#define HSTATUS_GVA 0x00000040
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 10c9f8b63b..b5f4264525 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -894,6 +894,19 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_has_ext(env, RVH)) {
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
+ if ((riscv_cpu_virt_enabled(env) ||
+ riscv_cpu_two_stage_lookup(env)) && tval) {
+ /*
+ * If we are writing a guest virtual address to stval, set
+ * this to 1. If we are trapping to VS we will set this to 0
+ * later.
+ */
+ env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1);
+ } else {
+ /* For other HS-mode traps, we set this to 0. */
+ env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
+ }
+
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
/*
@@ -904,6 +917,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
cause == IRQ_VS_EXT)
cause = cause - 1;
/* Trap to VS mode */
+ env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
riscv_cpu_swap_hypervisor_regs(env);
@@ -952,13 +966,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
#ifdef TARGET_RISCV32
env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
riscv_cpu_virt_enabled(env));
- env->mstatush = set_field(env->mstatush, MSTATUS_MTL,
- riscv_cpu_force_hs_excep_enabled(env));
+ if (riscv_cpu_virt_enabled(env) && tval) {
+ env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1);
+ }
#else
env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
riscv_cpu_virt_enabled(env));
- env->mstatus = set_field(env->mstatus, MSTATUS_MTL,
- riscv_cpu_force_hs_excep_enabled(env));
+ if (riscv_cpu_virt_enabled(env) && tval) {
+ env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
+ }
#endif
mtval2 = env->guest_phys_fault_addr;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0f035d33b1..f9ac21d687 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -403,10 +403,10 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
MSTATUS_TW;
#if defined(TARGET_RISCV64)
/*
- * RV32: MPV and MTL are not in mstatus. The current plan is to
+ * RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
*/
- mask |= MSTATUS_MTL | MSTATUS_MPV;
+ mask |= MSTATUS_MPV | MSTATUS_GVA;
#endif
mstatus = (mstatus & ~mask) | (val & mask);
@@ -432,7 +432,7 @@ static int write_mstatush(CPURISCVState *env, int csrno,
target_ulong val)
tlb_flush(env_cpu(env));
}
- val &= MSTATUS_MPV | MSTATUS_MTL;
+ val &= MSTATUS_MPV | MSTATUS_GVA;
env->mstatush = val;
--
2.27.0
- [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1, Alistair Francis, 2020/08/12
- [PATCH v3 01/13] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/08/12
- [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 03/13] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 04/13] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/08/12
- [PATCH v3 05/13] target/riscv: Convert MSTATUS MTL to GVA,
Alistair Francis <=
- [PATCH v3 06/13] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/08/12
- [PATCH v3 07/13] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/08/12
- [PATCH v3 08/13] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/08/12
- [PATCH v3 09/13] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/08/12
- [PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/08/12
- [PATCH v3 10/13] target/riscv: Only support little endian guests, Alistair Francis, 2020/08/12
- [PATCH v3 12/13] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/08/12
- [PATCH v3 13/13] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/08/12
- Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1, LIU Zhiwei, 2020/08/12