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Re: [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL |
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Date: |
Thu, 6 Aug 2020 11:36:49 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/6/20 3:46 AM, frank.chang@sifive.com wrote:
> + float flmul;
int8_t? It seems weird that the translator wouldn't also use...
> +/*
> + * Encode LMUL to lmul as following:
> + * LMUL vlmul lmul
> + * 1 000 0
> + * 2 001 1
> + * 4 010 2
> + * 8 011 3
> + * - 100 -
> + * 1/8 101 -3
> + * 1/4 110 -2
> + * 1/2 111 -1
> + */
> +static inline int32_t vext_lmul(uint32_t desc)
> {
> - return FIELD_EX32(simd_data(desc), VDATA, LMUL);
> + uint32_t lmul = FIELD_EX32(simd_data(desc), VDATA, LMUL);
> + return (int8_t)(lmul << 5) >> 5;
> }
... this encoding?
Oh, and sextract32(lmul, 0, 3) instead of those shifts.
r~
- [RFC v3 06/71] target/riscv: rvv-1.0: add translation-time vector context status, (continued)
- [RFC v3 06/71] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2020/08/06
- [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register, frank . chang, 2020/08/06
- [RFC v3 08/71] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2020/08/06
- [RFC v3 09/71] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2020/08/06
- [RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2020/08/06
- [RFC v3 11/71] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2020/08/06
- [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2020/08/06
- Re: [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL,
Richard Henderson <=
- [RFC v3 13/71] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/08/06
- [RFC v3 14/71] target/riscv: rvv-1.0: update check functions, frank . chang, 2020/08/06
- [RFC v3 16/71] target/riscv: add fp16 nan-box check generator function, frank . chang, 2020/08/06
- [RFC v3 15/71] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/08/06
- [RFC v3 17/71] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2020/08/06