Re: [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields f

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Re: [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields f

From:	Richard Henderson
Subject:	Re: [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register
Date:	Thu, 6 Aug 2020 11:30:51 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0

On 8/6/20 3:46 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> Remove VXRM and VXSAT fields from FCSR register as they are only
> presented in VCSR register.
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Actually, there's a related clause in fs() that should be removed:

    /* loose check condition for fcsr in vector extension */
    if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
        return 0;
    }


r~

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[RFC v3 00/71] target/riscv: support vector extension v1.0, frank . chang, 2020/08/06
- [RFC v3 01/71] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2020/08/06
- [RFC v3 02/71] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2020/08/06
- [RFC v3 03/71] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2020/08/06
- [RFC v3 04/71] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2020/08/06
- [RFC v3 05/71] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2020/08/06
  - Re: [RFC v3 05/71] target/riscv: rvv-1.0: introduce writable misa.v field, Richard Henderson, 2020/08/06
- [RFC v3 06/71] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2020/08/06
- [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register, frank . chang, 2020/08/06
  - Re: [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register, Richard Henderson, 2020/08/06
  - Re: [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register, Richard Henderson <=
- [RFC v3 08/71] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2020/08/06
- [RFC v3 09/71] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2020/08/06
- [RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2020/08/06
  - Re: [RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, Richard Henderson, 2020/08/06
- [RFC v3 11/71] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2020/08/06
- [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2020/08/06
  - Re: [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL, Richard Henderson, 2020/08/06
    - Re: [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL, Frank Chang, 2020/08/13
- [RFC v3 13/71] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/08/06
  - Re: [RFC v3 13/71] target/riscv: rvv-1.0: add VMA and VTA, Richard Henderson, 2020/08/06

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