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[Qemu-riscv] [PATCH v7 27/30] riscv: sifive_u: Instantiate OTP memory wi
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH v7 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number |
Date: |
Sat, 31 Aug 2019 19:53:08 -0700 |
This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- create sifive_u_otp block directly in the machine codes, instead
of calling sifive_u_otp_create()
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 9 +++++++++
include/hw/riscv/sifive_u.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index d970037..516093e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,6 +10,7 @@
* 1) CLINT (Core Level Interruptor)
* 2) PLIC (Platform Level Interrupt Controller)
* 3) PRCI (Power, Reset, Clock, Interrupt)
+ * 4) OTP (One-Time Programmable) memory with stored serial number
*
* This board currently generates devicetree dynamically that indicates at
least
* two harts and up to five harts.
@@ -64,10 +65,12 @@ static const struct MemmapEntry {
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
+ [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
};
+#define OTP_SERIAL 1
#define GEM_REVISION 0x10070109
static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
@@ -422,6 +425,9 @@ static void riscv_sifive_u_soc_init(Object *obj)
sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
TYPE_SIFIVE_U_PRCI);
+ sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
+ TYPE_SIFIVE_U_OTP);
+ qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
TYPE_CADENCE_GEM);
}
@@ -498,6 +504,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
+
for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
}
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index b41e730..7d9d901 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -22,6 +22,7 @@
#include "hw/net/cadence_gem.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/riscv/sifive_u_prci.h"
+#include "hw/riscv/sifive_u_otp.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
@@ -38,6 +39,7 @@ typedef struct SiFiveUSoCState {
RISCVHartArrayState u_cpus;
DeviceState *plic;
SiFiveUPRCIState prci;
+ SiFiveUOTPState otp;
CadenceGEMState gem;
} SiFiveUSoCState;
@@ -59,6 +61,7 @@ enum {
SIFIVE_U_PRCI,
SIFIVE_U_UART0,
SIFIVE_U_UART1,
+ SIFIVE_U_OTP,
SIFIVE_U_DRAM,
SIFIVE_U_GEM
};
--
2.7.4
- [Qemu-riscv] [PATCH v7 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, (continued)
- [Qemu-riscv] [PATCH v7 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 12/30] riscv: sifive_e: Drop sifive_mmio_emulate(), Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 16/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 19/30] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 24/30] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 21/30] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number,
Bin Meng <=
- [Qemu-riscv] [PATCH v7 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 30/30] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 28/30] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 25/30] riscv: roms: Update default bios for sifive_u machine, Bin Meng, 2019/08/31