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[Qemu-riscv] [PATCH v7 19/30] riscv: sifive: Implement PRCI model for FU
|
From: |
Bin Meng |
|
Subject: |
[Qemu-riscv] [PATCH v7 19/30] riscv: sifive: Implement PRCI model for FU540 |
|
Date: |
Sat, 31 Aug 2019 19:53:00 -0700 |
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v7: None
Changes in v6:
- fix incorrectly indented comment lines
- remove unneeded brackets around assignment
Changes in v5:
- change to use defines instead of enums
- change to use qemu_log_mask(LOG_GUEST_ERROR,...) in sifive_u_prci
- creating a 32-bit val variable and using that instead of casting
everywhere in sifive_u_prci_write()
- move all register initialization to sifive_u_prci_reset() function
- drop sifive_u_prci_create()
- s/codes that worked/code that works/g
Changes in v4:
- prefix all macros/variables/functions with SIFIVE_U/sifive_u
in the sifive_u_prci driver
Changes in v3: None
Changes in v2: None
hw/riscv/Makefile.objs | 1 +
hw/riscv/sifive_u_prci.c | 169 +++++++++++++++++++++++++++++++++++++++
include/hw/riscv/sifive_u_prci.h | 81 +++++++++++++++++++
3 files changed, 251 insertions(+)
create mode 100644 hw/riscv/sifive_u_prci.c
create mode 100644 include/hw/riscv/sifive_u_prci.h
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index c859697..b95bbd5 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o
obj-$(CONFIG_SIFIVE) += sifive_plic.o
obj-$(CONFIG_SIFIVE) += sifive_test.o
obj-$(CONFIG_SIFIVE_U) += sifive_u.o
+obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
obj-$(CONFIG_SIFIVE) += sifive_uart.o
obj-$(CONFIG_SPIKE) += spike.o
obj-$(CONFIG_RISCV_VIRT) += virt.o
diff --git a/hw/riscv/sifive_u_prci.c b/hw/riscv/sifive_u_prci.c
new file mode 100644
index 0000000..ade2a1c
--- /dev/null
+++ b/hw/riscv/sifive_u_prci.c
@@ -0,0 +1,169 @@
+/*
+ * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt)
+ *
+ * Copyright (c) 2019 Bin Meng <address@hidden>
+ *
+ * Simple model of the PRCI to emulate register reads made by the SDK BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/riscv/sifive_u_prci.h"
+
+static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int
size)
+{
+ SiFiveUPRCIState *s = opaque;
+
+ switch (addr) {
+ case SIFIVE_U_PRCI_HFXOSCCFG:
+ return s->hfxosccfg;
+ case SIFIVE_U_PRCI_COREPLLCFG0:
+ return s->corepllcfg0;
+ case SIFIVE_U_PRCI_DDRPLLCFG0:
+ return s->ddrpllcfg0;
+ case SIFIVE_U_PRCI_DDRPLLCFG1:
+ return s->ddrpllcfg1;
+ case SIFIVE_U_PRCI_GEMGXLPLLCFG0:
+ return s->gemgxlpllcfg0;
+ case SIFIVE_U_PRCI_GEMGXLPLLCFG1:
+ return s->gemgxlpllcfg1;
+ case SIFIVE_U_PRCI_CORECLKSEL:
+ return s->coreclksel;
+ case SIFIVE_U_PRCI_DEVICESRESET:
+ return s->devicesreset;
+ case SIFIVE_U_PRCI_CLKMUXSTATUS:
+ return s->clkmuxstatus;
+ }
+
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
+ __func__, (int)addr);
+
+ return 0;
+}
+
+static void sifive_u_prci_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ SiFiveUPRCIState *s = opaque;
+ uint32_t val32 = (uint32_t)val64;
+
+ switch (addr) {
+ case SIFIVE_U_PRCI_HFXOSCCFG:
+ s->hfxosccfg = val32;
+ /* OSC stays ready */
+ s->hfxosccfg |= SIFIVE_U_PRCI_HFXOSCCFG_RDY;
+ break;
+ case SIFIVE_U_PRCI_COREPLLCFG0:
+ s->corepllcfg0 = val32;
+ /* internal feedback */
+ s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
+ /* PLL stays locked */
+ s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
+ break;
+ case SIFIVE_U_PRCI_DDRPLLCFG0:
+ s->ddrpllcfg0 = val32;
+ /* internal feedback */
+ s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
+ /* PLL stays locked */
+ s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
+ break;
+ case SIFIVE_U_PRCI_DDRPLLCFG1:
+ s->ddrpllcfg1 = val32;
+ break;
+ case SIFIVE_U_PRCI_GEMGXLPLLCFG0:
+ s->gemgxlpllcfg0 = val32;
+ /* internal feedback */
+ s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
+ /* PLL stays locked */
+ s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
+ break;
+ case SIFIVE_U_PRCI_GEMGXLPLLCFG1:
+ s->gemgxlpllcfg1 = val32;
+ break;
+ case SIFIVE_U_PRCI_CORECLKSEL:
+ s->coreclksel = val32;
+ break;
+ case SIFIVE_U_PRCI_DEVICESRESET:
+ s->devicesreset = val32;
+ break;
+ case SIFIVE_U_PRCI_CLKMUXSTATUS:
+ s->clkmuxstatus = val32;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
+ __func__, (int)addr, (int)val64);
+ }
+}
+
+static const MemoryRegionOps sifive_u_prci_ops = {
+ .read = sifive_u_prci_read,
+ .write = sifive_u_prci_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+};
+
+static void sifive_u_prci_realize(DeviceState *dev, Error **errp)
+{
+ SiFiveUPRCIState *s = SIFIVE_U_PRCI(dev);
+
+ memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_prci_ops, s,
+ TYPE_SIFIVE_U_PRCI, SIFIVE_U_PRCI_REG_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+}
+
+static void sifive_u_prci_reset(DeviceState *dev)
+{
+ SiFiveUPRCIState *s = SIFIVE_U_PRCI(dev);
+
+ /* Initialize register to power-on-reset values */
+ s->hfxosccfg = SIFIVE_U_PRCI_HFXOSCCFG_RDY | SIFIVE_U_PRCI_HFXOSCCFG_EN;
+ s->corepllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF |
+ SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE |
+ SIFIVE_U_PRCI_PLLCFG0_LOCK;
+ s->ddrpllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF |
+ SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE |
+ SIFIVE_U_PRCI_PLLCFG0_LOCK;
+ s->gemgxlpllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF
|
+ SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE |
+ SIFIVE_U_PRCI_PLLCFG0_LOCK;
+ s->coreclksel = SIFIVE_U_PRCI_CORECLKSEL_HFCLK;
+}
+
+static void sifive_u_prci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = sifive_u_prci_realize;
+ dc->reset = sifive_u_prci_reset;
+}
+
+static const TypeInfo sifive_u_prci_info = {
+ .name = TYPE_SIFIVE_U_PRCI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SiFiveUPRCIState),
+ .class_init = sifive_u_prci_class_init,
+};
+
+static void sifive_u_prci_register_types(void)
+{
+ type_register_static(&sifive_u_prci_info);
+}
+
+type_init(sifive_u_prci_register_types)
diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h
new file mode 100644
index 0000000..60a2eab
--- /dev/null
+++ b/include/hw/riscv/sifive_u_prci.h
@@ -0,0 +1,81 @@
+/*
+ * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface
+ *
+ * Copyright (c) 2019 Bin Meng <address@hidden>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SIFIVE_U_PRCI_H
+#define HW_SIFIVE_U_PRCI_H
+
+#define SIFIVE_U_PRCI_HFXOSCCFG 0x00
+#define SIFIVE_U_PRCI_COREPLLCFG0 0x04
+#define SIFIVE_U_PRCI_DDRPLLCFG0 0x0C
+#define SIFIVE_U_PRCI_DDRPLLCFG1 0x10
+#define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C
+#define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20
+#define SIFIVE_U_PRCI_CORECLKSEL 0x24
+#define SIFIVE_U_PRCI_DEVICESRESET 0x28
+#define SIFIVE_U_PRCI_CLKMUXSTATUS 0x2C
+
+/*
+ * Current FU540-C000 manual says ready bit is at bit 29, but
+ * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
+ * We have to trust the actual code that works.
+ *
+ * see https://github.com/sifive/freedom-u540-c000-bootloader
+ */
+
+#define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30)
+#define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31)
+
+/* xxxPLLCFG0 register bits */
+#define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0)
+#define SIFIVE_U_PRCI_PLLCFG0_DIVF (31 << 6)
+#define SIFIVE_U_PRCI_PLLCFG0_DIVQ (3 << 15)
+#define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25)
+#define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31)
+
+/* xxxPLLCFG1 register bits */
+#define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24)
+
+/* coreclksel register bits */
+#define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0)
+
+
+#define SIFIVE_U_PRCI_REG_SIZE 0x1000
+
+#define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci"
+
+#define SIFIVE_U_PRCI(obj) \
+ OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI)
+
+typedef struct SiFiveUPRCIState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion mmio;
+ uint32_t hfxosccfg;
+ uint32_t corepllcfg0;
+ uint32_t ddrpllcfg0;
+ uint32_t ddrpllcfg1;
+ uint32_t gemgxlpllcfg0;
+ uint32_t gemgxlpllcfg1;
+ uint32_t coreclksel;
+ uint32_t devicesreset;
+ uint32_t clkmuxstatus;
+} SiFiveUPRCIState;
+
+#endif /* HW_SIFIVE_U_PRCI_H */
--
2.7.4
- [Qemu-riscv] [PATCH v7 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array, (continued)
- [Qemu-riscv] [PATCH v7 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 14/30] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 23/30] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 18/30] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 12/30] riscv: sifive_e: Drop sifive_mmio_emulate(), Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 16/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 19/30] riscv: sifive: Implement PRCI model for FU540,
Bin Meng <=
- [Qemu-riscv] [PATCH v7 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 24/30] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 21/30] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 30/30] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 28/30] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/31
- [Qemu-riscv] [PATCH v7 25/30] riscv: roms: Update default bios for sifive_u machine, Bin Meng, 2019/08/31