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Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/7] target/riscv: Create functi
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From: |
Bin Meng |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled |
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Date: |
Fri, 16 Aug 2019 21:59:11 +0800 |
On Fri, Aug 16, 2019 at 5:42 AM Alistair Francis
<address@hidden> wrote:
>
> Let's create a function that tests if floating point support is
> enabled. We can then protect all floating point operations based on if
> they are enabled.
>
> This patch so far doesn't change anything, it's just preparing for the
> Hypervisor support for floating point operations.
>
> Signed-off-by: Alistair Francis <address@hidden>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> Reviewed-by: Christophe de Dinechin <address@hidden>
> Reviewed-by: Chih-Min Chao <address@hidden>
> ---
> target/riscv/cpu.h | 6 +++++-
> target/riscv/cpu_helper.c | 10 ++++++++++
> target/riscv/csr.c | 20 +++++++++++---------
> 3 files changed, 26 insertions(+), 10 deletions(-)
>
Reviewed-by: Bin Meng <address@hidden>
- [Qemu-riscv] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 1/7] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/08/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled,
Bin Meng <=
- [Qemu-riscv] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 5/7] target/riscv: Use both register name and ABI name, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong, Alistair Francis, 2019/08/15