[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask
|
From: |
Alistair Francis |
|
Subject: |
[Qemu-riscv] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask |
|
Date: |
Thu, 15 Aug 2019 14:35:01 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 2789215b5e..f767ad24be 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -335,7 +335,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
* RV32: MPV and MTL are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
*/
- mask |= MSTATUS_MPP | MSTATUS_MPV;
+ mask |= MSTATUS_MTL | MSTATUS_MPV;
#endif
}
--
2.22.0
- [Qemu-riscv] [PATCH v3 1/7] target/riscv: Don't set write permissions on dirty PTEs, (continued)
- [Qemu-riscv] [PATCH v3 1/7] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 5/7] target/riscv: Use both register name and ABI name, Alistair Francis, 2019/08/15
- [Qemu-riscv] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask,
Alistair Francis <=
- [Qemu-riscv] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong, Alistair Francis, 2019/08/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2, no-reply, 2019/08/15