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Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 22/28] riscv: sifive_u: Generate
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From: |
Alistair Francis |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree |
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Date: |
Sun, 11 Aug 2019 10:19:09 -0700 |
On Sun, Aug 11, 2019 at 1:13 AM Bin Meng <address@hidden> wrote:
>
> The Linux kernel SiFive UART driver expects an aliases node to be
> present in the device tree, from which the driver extracts the port
> number from "serial#" in the aliases node.
>
> Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> hw/riscv/sifive_u.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7eb2b7e..0c1a89f 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -284,6 +284,8 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> if (cmdline) {
> qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
> }
> + qemu_fdt_add_subnode(fdt, "/aliases");
> + qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
> g_free(nodename);
> }
>
> --
> 2.7.4
>
>
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size, (continued)
- [Qemu-riscv] [PATCH v3 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/11
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree,
Alistair Francis <=
- [Qemu-riscv] [PATCH v3 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 23/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/11