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[Qemu-riscv] [PATCH v3 09/28] riscv: sifive_u: Update UART base addresse
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH v3 09/28] riscv: sifive_u: Update UART base addresses and IRQs |
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Date: |
Sun, 11 Aug 2019 01:06:42 -0700 |
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
---
Changes in v3:
- update IRQ numbers of both UARTs to match hardware as well
Changes in v2: None
hw/riscv/sifive_u.c | 4 ++--
include/hw/riscv/sifive_u.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 16ab95c..f24ec2e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -61,8 +61,8 @@ static const struct MemmapEntry {
[SIFIVE_U_MROM] = { 0x1000, 0x11000 },
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
- [SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
- [SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
+ [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
+ [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
};
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 650bc4c..d0d8528 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -58,8 +58,8 @@ enum {
};
enum {
- SIFIVE_U_UART0_IRQ = 3,
- SIFIVE_U_UART1_IRQ = 4,
+ SIFIVE_U_UART0_IRQ = 4,
+ SIFIVE_U_UART1_IRQ = 5,
SIFIVE_U_GEM_IRQ = 0x35
};
--
2.7.4
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 04/28] riscv: hart: Extract hart realize to a separate routine, (continued)
- [Qemu-riscv] [PATCH v3 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 09/28] riscv: sifive_u: Update UART base addresses and IRQs,
Bin Meng <=
- [Qemu-riscv] [PATCH v3 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/11