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Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 12/28] riscv: sifive_e: prci: Fi
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From: |
Philippe Mathieu-Daudé |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming |
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Date: |
Wed, 7 Aug 2019 11:49:23 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 |
On 8/7/19 9:45 AM, Bin Meng wrote:
> It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN
> for hfxosccfg register programming.
>
> Signed-off-by: Bin Meng <address@hidden>
> Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
>
> Changes in v2: None
>
> hw/riscv/sifive_e_prci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
> index acb914d..c906f11 100644
> --- a/hw/riscv/sifive_e_prci.c
> +++ b/hw/riscv/sifive_e_prci.c
> @@ -89,7 +89,7 @@ static void sifive_prci_init(Object *obj)
> sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
>
> s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
> - s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
> + s->hfxosccfg = (SIFIVE_PRCI_HFXOSCCFG_RDY | SIFIVE_PRCI_HFXOSCCFG_EN);
> s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS |
> SIFIVE_PRCI_PLLCFG_LOCK);
> s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1;
>
- [Qemu-riscv] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, (continued)
- [Qemu-riscv] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/07
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Alistair Francis, 2019/08/09
- [Qemu-riscv] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/07