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[Qemu-riscv] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2 |
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Date: |
Wed, 7 Aug 2019 00:45:03 -0700 |
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng <address@hidden>
---
Changes in v2:
- update the file header to indicate at least 2 harts are created
hw/riscv/sifive_u.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 821f1d5..91f3c76 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,8 +10,8 @@
* 1) CLINT (Core Level Interruptor)
* 2) PLIC (Platform Level Interrupt Controller)
*
- * This board currently generates devicetree dynamically that indicates at most
- * five harts.
+ * This board currently generates devicetree dynamically that indicates at
least
+ * two harts and up to five harts.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -429,6 +429,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
* management CPU.
*/
mc->max_cpus = 5;
+ /* It is not useful if we only have one management CPU */
+ mc->min_cpus = 2;
}
DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
--
2.7.4
- [Qemu-riscv] [PATCH v2 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 01/28] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 04/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2,
Bin Meng <=
- [Qemu-riscv] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/07