Re: [Qemu-riscv] [Qemu-devel] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names

[Alistair Francis]

On Mon, Jul 29, 2019 at 8:19 AM Chih-Min Chao <address@hidden> wrote:
>
>
> On Fri, Jul 26, 2019 at 2:56 AM Alistair Francis <address@hidden> wrote:
>>
>> From: Atish Patra <address@hidden>
>>
>> As per the RISC-V spec, Floating Point registers are named as f0..f31
>> so lets fix the register names accordingly.
>>
>> Signed-off-by: Atish Patra <address@hidden>
>> Signed-off-by: Alistair Francis <address@hidden>
>> ---
>>  target/riscv/cpu.c | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index f8d07bd20a..af1e9b7690 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -40,10 +40,10 @@ const char * const riscv_int_regnames[] = {
>>  };
>>
>>  const char * const riscv_fpr_regnames[] = {
>> -  "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
>> -  "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
>> -  "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
>> -  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
>> +  "f0", "f1", "f2",  "f3",  "f4", "f5", "f6", "f7",
>> +  "f8", "f9", "f10",  "f11",  "f12", "f13", "f14", "f15",
>> +  "f16", "f17", "f18",  "f19",  "f20", "f21", "f22", "f23",
>> +  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
>>  };
>
>
> Could you indicate the section of the spec ?

Chapter 11: "“F” Standard Extension for Single-Precision
Floating-Point, Version 2.2", section 11.1, Figure 11.1 shows f0 -
f32.

> By chapter 20 of user spec, the patch changes the floating register name to 
> architecture name but leave the integer register use the ABI name.

You mean the Packed-SIMD extension?

Alistair

>
> chihmin
>>
>>  const char * const riscv_excp_names[] = {
>> --
>> 2.22.0
>>
>>