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Re: [Qemu-riscv] [PATCH-4.2 v1 4/6] target/riscv: Create function to tes
From: |
Alistair Francis |
Subject: |
Re: [Qemu-riscv] [PATCH-4.2 v1 4/6] target/riscv: Create function to test if FP is enabled |
Date: |
Tue, 30 Jul 2019 11:32:13 -0700 |
On Mon, Jul 29, 2019 at 9:56 AM Chih-Min Chao <address@hidden> wrote:
>
>
>
> On Fri, Jul 26, 2019 at 2:55 AM Alistair Francis <address@hidden> wrote:
>>
>> Let's creaate a function that tests if floating point support is
>> enabled. We can then protect all floating point operations based on if
>> they are enabled.
>>
>> This patch so far doesn't change anything, it's just preparing for the
>> Hypervisor support for floating point operations.
>>
>> Signed-off-by: Alistair Francis <address@hidden>
>> ---
>> target/riscv/cpu.h | 6 +++++-
>> target/riscv/cpu_helper.c | 10 ++++++++++
>> target/riscv/csr.c | 19 ++++++++++---------
>> 3 files changed, 25 insertions(+), 10 deletions(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 0adb307f32..2dc9b17678 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -255,6 +255,7 @@ void riscv_cpu_do_interrupt(CPUState *cpu);
>> int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
>> int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
>> bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
>> +bool riscv_cpu_fp_enabled(CPURISCVState *env);
>> int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
>> hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
>> void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>> @@ -298,7 +299,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
>> *env, target_ulong *pc,
>> #ifdef CONFIG_USER_ONLY
>> *flags = TB_FLAGS_MSTATUS_FS;
>> #else
>> - *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
>> + *flags = cpu_mmu_index(env, 0);
>> + if (riscv_cpu_fp_enabled(env)) {
>> + *flags |= env->mstatus & MSTATUS_FS;
>> + }
>> #endif
>> }
>>
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index f027be7f16..225e407cff 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -71,6 +71,16 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int
>> interrupt_request)
>>
>> #if !defined(CONFIG_USER_ONLY)
>>
>> +/* Return true is floating point support is currently enabled */
>> +bool riscv_cpu_fp_enabled(CPURISCVState *env)
>> +{
>> + if (env->mstatus & MSTATUS_FS) {
>> + return true;
>> + }
>> +
>> + return false;
>> +}
>> +
>> int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
>> {
>> CPURISCVState *env = &cpu->env;
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index af3b762c8b..7b73b73cf7 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations
>> *ops)
>> static int fs(CPURISCVState *env, int csrno)
>> {
>> #if !defined(CONFIG_USER_ONLY)
>> - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
>> return -1;
>> }
>> #endif
>> @@ -108,7 +108,7 @@ static int pmp(CPURISCVState *env, int csrno)
>> static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>> {
>> #if !defined(CONFIG_USER_ONLY)
>> - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
>> return -1;
>> }
>> #endif
>> @@ -119,7 +119,7 @@ static int read_fflags(CPURISCVState *env, int csrno,
>> target_ulong *val)
>> static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>> {
>> #if !defined(CONFIG_USER_ONLY)
>> - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
>> return -1;
>> }
>> env->mstatus |= MSTATUS_FS;
>> @@ -131,7 +131,7 @@ static int write_fflags(CPURISCVState *env, int csrno,
>> target_ulong val)
>> static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
>> {
>> #if !defined(CONFIG_USER_ONLY)
>> - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
>> return -1;
>> }
>> #endif
>> @@ -142,7 +142,7 @@ static int read_frm(CPURISCVState *env, int csrno,
>> target_ulong *val)
>> static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
>> {
>> #if !defined(CONFIG_USER_ONLY)
>> - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
>> return -1;
>> }
>> env->mstatus |= MSTATUS_FS;
>> @@ -154,7 +154,7 @@ static int write_frm(CPURISCVState *env, int csrno,
>> target_ulong val)
>> static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>> {
>> #if !defined(CONFIG_USER_ONLY)
>> - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
>> return -1;
>> }
>> #endif
>> @@ -166,7 +166,7 @@ static int read_fcsr(CPURISCVState *env, int csrno,
>> target_ulong *val)
>> static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
>> {
>> #if !defined(CONFIG_USER_ONLY)
>> - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
>> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
>> return -1;
>> }
>> env->mstatus |= MSTATUS_FS;
>> @@ -307,6 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,
>> target_ulong val)
>> {
>> target_ulong mstatus = env->mstatus;
>> target_ulong mask = 0;
>> + int dirty;
>>
>> /* flush tlb on mstatus fields that affect VM */
>> if (env->priv_ver <= PRIV_VERSION_1_09_1) {
>> @@ -340,8 +341,8 @@ static int write_mstatus(CPURISCVState *env, int csrno,
>> target_ulong val)
>>
>> mstatus = (mstatus & ~mask) | (val & mask);
>>
>> - int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
>> - ((mstatus & MSTATUS_XS) == MSTATUS_XS);
>> + dirty = riscv_cpu_fp_enabled(env) |
>> + ((mstatus & MSTATUS_XS) == MSTATUS_XS);
>
>
> FS are 2bits
> original:
> only 3 is true
> new
> 1, 2, 3 all make dirty true
>
> Since only 3 means dirty, keeps this part unchanged should be reasonable.
Good point, I have updated this.
Alistair
>
> chihmin
>
>> mstatus = set_field(mstatus, MSTATUS_SD, dirty);
>> env->mstatus = mstatus;
>>
>> --
>> 2.22.0
>>
>>
- Re: [Qemu-riscv] [PATCH-4.2 v1 2/6] target/riscv: Remove strict perm checking for CSR R/W, (continued)
[Qemu-riscv] [PATCH-4.2 v1 3/6] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/07/25
[Qemu-riscv] [PATCH-4.2 v1 4/6] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/07/25
[Qemu-riscv] [PATCH-4.2 v1 5/6] target/riscv: Update the Hypervisor CSRs to v0.4, Alistair Francis, 2019/07/25
[Qemu-riscv] [PATCH-4.2 v1 6/6] target/riscv: Fix Floating Point register names, Alistair Francis, 2019/07/25