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[PATCH 24/26] target/ppc: Implement LDBAR, TTR SPRs
From: |
Nicholas Piggin |
Subject: |
[PATCH 24/26] target/ppc: Implement LDBAR, TTR SPRs |
Date: |
Fri, 19 Jan 2024 01:06:42 +1000 |
LDBAR, TTR are a Power-specific SPRs. These simple implementations
are enough for IBM proprietary firmware for now.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 10 ++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 8397ddaf18..b6a955b9b7 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2088,6 +2088,7 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_DEXCR (0x33C)
#define SPR_IC (0x350)
#define SPR_VTB (0x351)
+#define SPR_LDBAR (0x352)
#define SPR_MMCRC (0x353)
#define SPR_PSSCR (0x357)
#define SPR_440_INV0 (0x370)
@@ -2134,6 +2135,7 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_440_IVLIM (0x399)
#define SPR_TSCR (0x399)
#define SPR_750_DMAU (0x39A)
+#define SPR_POWER_TTR (0x39A)
#define SPR_750_DMAL (0x39B)
#define SPR_440_RSTCFG (0x39B)
#define SPR_BOOKE_DCDBTRL (0x39C)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 0a42e14338..31d535d501 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5695,6 +5695,16 @@ static void register_power_common_book4_sprs(CPUPPCState
*env)
&spr_access_nop, &spr_write_generic,
&spr_access_nop, &spr_write_generic,
0x00000000);
+ spr_register_hv(env, SPR_LDBAR, "LDBAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_core_lpar_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_POWER_TTR, "TTR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_core_write_generic,
+ 0x00000000);
#endif
}
--
2.42.0
- [PATCH 10/26] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines, (continued)
- [PATCH 10/26] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines, Nicholas Piggin, 2024/01/18
- [PATCH 11/26] pnv/chiptod: Implement the ChipTOD to Core transfer, Nicholas Piggin, 2024/01/18
- [PATCH 12/26] target/ppc: Implement core timebase state machine and TFMR, Nicholas Piggin, 2024/01/18
- [PATCH 13/26] target/ppc: Add SMT support to time facilities, Nicholas Piggin, 2024/01/18
- [PATCH 14/26] target/ppc: Add new hflags to support BHRB, Nicholas Piggin, 2024/01/18
- [PATCH 15/26] target/ppc: Add recording of taken branches to BHRB, Nicholas Piggin, 2024/01/18
- [PATCH 17/26] target/ppc: Add migration support for BHRB, Nicholas Piggin, 2024/01/18
- [PATCH 18/26] target/ppc: BookE DECAR SPR is 32-bit, Nicholas Piggin, 2024/01/18
- [PATCH 16/26] target/ppc: Add clrbhrb and mfbhrbe instructions, Nicholas Piggin, 2024/01/18
- [PATCH 22/26] target/ppc: Add SMT support to simple SPRs, Nicholas Piggin, 2024/01/18
- [PATCH 24/26] target/ppc: Implement LDBAR, TTR SPRs,
Nicholas Piggin <=
- [PATCH 23/26] target/ppc: Add SMT support to PTCR SPR, Nicholas Piggin, 2024/01/18
- [PATCH 19/26] target/ppc: Wire up BookE ATB registers for e500 family, Nicholas Piggin, 2024/01/18
- [PATCH 20/26] target/ppc: Add PPR32 SPR, Nicholas Piggin, 2024/01/18
- [PATCH 21/26] target/ppc: add helper to write per-LPAR SPRs, Nicholas Piggin, 2024/01/18
- [PATCH 26/26] target/ppc: add SMT support to msgsnd broadcast, Nicholas Piggin, 2024/01/18
- [PATCH 25/26] target/ppc: Implement SPRC/SPRD SPRs, Nicholas Piggin, 2024/01/18
- Re: [PATCH 00/26] target/ppc: TCG improvements and fixes, Cédric Le Goater, 2024/01/19