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[PULL 31/41] target/ppc: books: External interrupt cleanup
From: |
Cédric Le Goater |
Subject: |
[PULL 31/41] target/ppc: books: External interrupt cleanup |
Date: |
Mon, 31 Jan 2022 12:08:01 +0100 |
From: Fabiano Rosas <farosas@linux.ibm.com>
Since this is now BookS only, we can simplify the code a bit and check
has_hv_mode instead of enumerating the exception models. LPES0 does
not make sense if there is no MSR_HV.
Note that QEMU does not support HV mode on 970 and POWER5+ so we don't
set MSR_HV in msr_mask.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220124184605.999353-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 30 +++++++-----------------------
1 file changed, 7 insertions(+), 23 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index be8c64a0cde9..e0d6287c4e88 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -644,39 +644,23 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
bool lpes0;
- cs = CPU(cpu);
-
/*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
+ * LPES0 is only taken into consideration if we support HV
+ * mode for this CPU.
*/
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
+ if (!env->has_hv_mode) {
+ break;
}
+ lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+
if (!lpes0) {
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
}
- if (env->mpic_proxy) {
- /* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
- }
+
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
--
2.34.1
- [PULL 41/41] target/ppc: Remove support for the PowerPC 602 CPU, (continued)
- [PULL 41/41] target/ppc: Remove support for the PowerPC 602 CPU, Cédric Le Goater, 2022/01/31
- [PULL 24/41] target/ppc: 405: Data Storage exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 40/41] target/ppc: 74xx: Set SRRs directly in exception code, Cédric Le Goater, 2022/01/31
- [PULL 07/41] ppc/xive: check return value of ldq_be_dma(), Cédric Le Goater, 2022/01/31
- [PULL 02/41] target/ppc: 603: fix restore of GPRs 0-3 on rfi, Cédric Le Goater, 2022/01/31
[PULL 36/41] target/ppc: 74xx: External interrupt cleanup, Cédric Le Goater, 2022/01/31
[PULL 31/41] target/ppc: books: External interrupt cleanup,
Cédric Le Goater <=
[PULL 28/41] target/ppc: Introduce powerpc_excp_books, Cédric Le Goater, 2022/01/31
[PULL 39/41] target/ppc: 74xx: System Reset interrupt cleanup, Cédric Le Goater, 2022/01/31
[PULL 15/41] target/ppc: 405: Add missing MSR_ME bit, Cédric Le Goater, 2022/01/31
[PULL 37/41] target/ppc: 74xx: Program exception cleanup, Cédric Le Goater, 2022/01/31
[PULL 17/41] target/ppc: Simplify powerpc_excp_40x, Cédric Le Goater, 2022/01/31
[PULL 22/41] target/ppc: 405: Alignment exception cleanup, Cédric Le Goater, 2022/01/31
[PULL 21/41] target/ppc: 405: System call exception cleanup, Cédric Le Goater, 2022/01/31
[PULL 34/41] target/ppc: Simplify powerpc_excp_74xx, Cédric Le Goater, 2022/01/31
[PULL 09/41] spapr.c: check bus != NULL in spapr_get_fw_dev_path(), Cédric Le Goater, 2022/01/31
[PULL 04/41] ppc/pnv: Fail DMA access if page permissions are not correct, Cédric Le Goater, 2022/01/31