Help with ppc e500 tlb usage

[Jesse Millwood]

Hello,

I'm trying to get the e500 to set the initial tlb entry to mirror what the 
platform expects. I have made some changes that seem to follow the e500 Core 
Reference Manual better, but they do not seem to work at runtime. I am 
wondering if someone can point me to where the tlb is actually used to reserve 
memory.

Currently, the page size is set relative to the device tree size from the boot 
info[0]. However, different platforms that use the e500 have different default 
settings.

I have added a new field to the PPCE500MachineClass and the CPUPPCState, 
allowing the platform author to set the initial_tlb_size_kib from the 
platform's machine class init function. The value then can be accessed in the 
booke206_initial_map_tsize function that sets returns the page size for the 
TSIZE field of the MAS1 register. I have kept the original functionality in 
case the platform doesn't set the field. My new method for computing the TSIZE 
field from a requested page size takes advantage of the page size being defined 
as 4^TSIZE KiB and being equal to 2^(2*TSIZE) KiB. So with the page size 
requested, you can find the bit index that is set with clz64 and then divide by 
2. This will give the bit field as defined in the e500 core reference manual.

Using my method of setting the TSIZE bits in booke206_initial_map_tsize, 
mmubooke_create_initial_mapping shifts the returned value and uses it to set 
the initial MAS1 register.

I found one other issue that doesn't match up with the e500 Core Reference 
Manual [1]:

The shift for the TSIZE is off by 1 [2]. The TSIZE field is bits 52-55 with a 
reserved field taking up 56-63. The reserved space should be 8 bits not 7. 

My issue comes at runtime. If I compile qemu with my changes and tell it to 
have a 4GiB initial tlb map size, the monitor command "info tlb" only reports a 
2MiB entry. This also makes it so my binary can't run because the window isn't 
big enough.

I can see that the tlb mas regsiters get set in the 
mmubooke_create_initial_mapping[3] but I am having trouble finding where that 
tlb struct is used afterwards. If anyone has any pointers, I'd appreciate it.


I have attached my patches in case anyone is interested in what I've done.

Thanks,
Jesse

0: https://gitlab.com/qemu-project/qemu/-/blob/master/hw/ppc/e500.c#L662 
1: E500 CORE REFERENCE MANUAL: 2.12.5.2 MAS Register 1 (MAS1) (also attached)
2: https://gitlab.com/qemu-project/qemu/-/blob/master/target/ppc/cpu.h#L847 
3: https://gitlab.com/qemu-project/qemu/-/blob/master/hw/ppc/e500.c#L687

E500CORERM MAS1 Fields.png
Description: E500CORERM MAS1 Fields.png

0004-ppc-e500-Set-the-initial-tlb-size-to-4GiB-on-the-e50.patch
Description: 0004-ppc-e500-Set-the-initial-tlb-size-to-4GiB-on-the-e50.patch

0003-ppc-e500-Calculate-the-TSIZE-variable-based-on-what-.patch
Description: 0003-ppc-e500-Calculate-the-TSIZE-variable-based-on-what-.patch

0002-ppc-e500-Add-field-to-PPCE500MachineClass-and-CPUPPC.patch
Description: 0002-ppc-e500-Add-field-to-PPCE500MachineClass-and-CPUPPC.patch

0001-e500-Fix-TSIZE-shift-constant.patch
Description: 0001-e500-Fix-TSIZE-shift-constant.patch