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Re: [PATCH qemu] spapr: Force 32bit when resetting a core


From: Greg Kurz
Subject: Re: [PATCH qemu] spapr: Force 32bit when resetting a core
Date: Fri, 7 Jan 2022 12:57:47 +0100

On Fri, 7 Jan 2022 18:24:23 +1100
Alexey Kardashevskiy <aik@ozlabs.ru> wrote:

> "PowerPC Processor binding to IEEE 1275" says in
> "8.2.1. Initial Register Values" that the initial state is defined as
> 32bit so do it for both SLOF and VOF.
> 
> This should not cause behavioral change as SLOF switches to 64bit very
> early anyway. 

Only one CPU goes through SLOF. What about the other ones, including
hot plugged CPUs ?

> As nothing enforces LE anywhere, this drops it for VOF.
> 
> The goal is to make VOF work with TCG as otherwise it barfs with
> qemu: fatal: TCG hflags mismatch (current:0x6c000004 rebuilt:0x6c000000)
> 
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
>  hw/ppc/spapr_cpu_core.c | 5 +++++
>  hw/ppc/spapr_vof.c      | 2 --
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index a57ba70a8781..a781e97f8d1d 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -37,6 +37,11 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu)
>  
>      cpu_reset(cs);
>  
> +    /*
> +     * "PowerPC Processor binding to IEEE 1275" defines the initial MSR state
> +     * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
> +     */
> +    env->msr &= ~(1ULL << MSR_SF);
>      env->spr[SPR_HIOR] = 0;
>  
>      lpcr = env->spr[SPR_LPCR];
> diff --git a/hw/ppc/spapr_vof.c b/hw/ppc/spapr_vof.c
> index 40ce8fe0037c..a33f940c32bb 100644
> --- a/hw/ppc/spapr_vof.c
> +++ b/hw/ppc/spapr_vof.c
> @@ -88,8 +88,6 @@ void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, 
> Error **errp)
>      spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT,
>                                stack_ptr, spapr->initrd_base,
>                                spapr->initrd_size);
> -    /* VOF is 32bit BE so enforce MSR here */
> -    first_ppc_cpu->env.msr &= ~((1ULL << MSR_SF) | (1ULL << MSR_LE));
>  
>      /*
>       * At this point the expected allocation map is:




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