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Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface
From: |
David Gibson |
Subject: |
Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface |
Date: |
Tue, 31 Mar 2020 14:14:07 +1100 |
On Tue, Mar 31, 2020 at 02:07:42PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 26/03/2020 01:41, Nicholas Piggin wrote:
> > This implements the NMI interface for the PNV machine, similarly to
> > commit 3431648272d ("spapr: Add support for new NMI interface") for
> > SPAPR.
> >
> > Signed-off-by: Nicholas Piggin <address@hidden>
> > ---
> > hw/ppc/pnv.c | 30 +++++++++++++++++++++++++++++-
> > 1 file changed, 29 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index b75ad06390..671535ebe6 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -27,6 +27,7 @@
> > #include "sysemu/runstate.h"
> > #include "sysemu/cpus.h"
> > #include "sysemu/device_tree.h"
> > +#include "sysemu/hw_accel.h"
> > #include "target/ppc/cpu.h"
> > #include "qemu/log.h"
> > #include "hw/ppc/fdt.h"
> > @@ -34,6 +35,7 @@
> > #include "hw/ppc/pnv.h"
> > #include "hw/ppc/pnv_core.h"
> > #include "hw/loader.h"
> > +#include "hw/nmi.h"
> > #include "exec/address-spaces.h"
> > #include "qapi/visitor.h"
> > #include "monitor/monitor.h"
> > @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool
> > value, Error **errp)
> > }
> > }
> >
> > +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
> > +{
> > + PowerPCCPU *cpu = POWERPC_CPU(cs);
> > + CPUPPCState *env = &cpu->env;
> > +
> > + cpu_synchronize_state(cs);
> > + ppc_cpu_do_system_reset(cs);
> > + /*
> > + * SRR1[42:45] is set to 0100 which the ISA defines as implementation
> > + * dependent. POWER processors use this for xscom triggered interrupts,
> > + * which come from the BMC or NMI IPIs.
> > + */
> > + env->spr[SPR_SRR1] |= PPC_BIT(43);
> > +}
> > +
> > +static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
> > +{
> > + CPUState *cs;
> > +
> > + CPU_FOREACH(cs) {
> > + async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
> > + }
> > +}
> > +
> > static void pnv_machine_class_init(ObjectClass *oc, void *data)
> > {
> > MachineClass *mc = MACHINE_CLASS(oc);
> > InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
> > + NMIClass *nc = NMI_CLASS(oc);
> >
> > mc->desc = "IBM PowerNV (Non-Virtualized)";
> > mc->init = pnv_init;
> > @@ -1975,6 +2002,7 @@ static void pnv_machine_class_init(ObjectClass *oc,
> > void *data)
> > mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
> > mc->default_ram_id = "pnv.ram";
> > ispc->print_info = pnv_pic_print_info;
> > + nc->nmi_monitor_handler = pnv_nmi;
> >
> > object_class_property_add_bool(oc, "hb-mode",
> > pnv_machine_get_hb, pnv_machine_set_hb,
> > @@ -2038,7 +2066,7 @@ static const TypeInfo types[] = {
> > .class_size = sizeof(PnvMachineClass),
> > .interfaces = (InterfaceInfo[]) {
> > { TYPE_INTERRUPT_STATS_PROVIDER },
> > - { },
> > + { TYPE_NMI },
>
>
> The interface list must end with {}, otherwise QEMU crashes very early.
> Thanks,
I've fixed that inline now.
>
>
> > },
> > },
> > {
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [PATCH 0/5] ppc: sreset and machine check injection, Nicholas Piggin, 2020/03/25
- [PATCH 1/5] ppc/spapr: tweak change system reset helper, Nicholas Piggin, 2020/03/25
- [PATCH 2/5] ppc/pnv: Add support for NMI interface, Nicholas Piggin, 2020/03/25
- [PATCH 3/5] nmi: add MCE class for implementing machine check injection commands, Nicholas Piggin, 2020/03/25
- [PATCH 4/5] ppc/spapr: Implement mce injection, Nicholas Piggin, 2020/03/25
- [PATCH 5/5] ppc/pnv: Implement mce injection, Nicholas Piggin, 2020/03/25
- Re: [PATCH 0/5] ppc: sreset and machine check injection, Cédric Le Goater, 2020/03/25