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[PATCH 9/9] ppc/xive: Check V bit in TM_PULL_POOL_CTX
From: |
Cédric Le Goater |
Subject: |
[PATCH 9/9] ppc/xive: Check V bit in TM_PULL_POOL_CTX |
Date: |
Mon, 7 Oct 2019 10:41:02 +0200 |
A context should be 'valid' when pulled from the thread interrupt
context registers.
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/intc/xive.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 143418c232a2..91eb7789f329 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -377,6 +377,11 @@ static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr
offset,
qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo);
+ if (!vo) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n",
+ nvt_blk, nvt_idx);
+ }
+
/* Invalidate CAM line */
qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
xive_tctx_set_os_cam(tctx, qw1w2_new);
--
2.21.0
- [PATCH 3/9] ppc/xive: Record the IPB in the associated NVT, (continued)
- [PATCH 3/9] ppc/xive: Record the IPB in the associated NVT, Cédric Le Goater, 2019/10/07
- [PATCH 2/9] ppc/pnv: Use address_space_stq_be() when triggering an interrupt from PSI, Cédric Le Goater, 2019/10/07
- [PATCH 8/9] ppc/xive: Introduce OS CAM line helpers, Cédric Le Goater, 2019/10/07
- [PATCH 6/9] ppc/pnv: Dump the XIVE NVT table, Cédric Le Goater, 2019/10/07
- [PATCH 7/9] ppc/pnv: Quiesce some XIVE errors, Cédric Le Goater, 2019/10/07
- [PATCH 1/9] ppc/pnv: Improve trigger data definition, Cédric Le Goater, 2019/10/07
- [PATCH 9/9] ppc/xive: Check V bit in TM_PULL_POOL_CTX,
Cédric Le Goater <=
- [PATCH 5/9] ppc/pnv: Remove pnv_xive_vst_size() routine, Cédric Le Goater, 2019/10/07
- Re: [PATCH 0/9] ppc/pnv: XIVE cleanup and fixes, Cédric Le Goater, 2019/10/21