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[Qemu-ppc] [PULL 3/8] target/ppc: Consolidate 64-bit server processor de
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 3/8] target/ppc: Consolidate 64-bit server processor detection in a helper |
Date: |
Fri, 29 Mar 2019 14:29:24 +1100 |
From: Greg Kurz <address@hidden>
We use PPC_SEGMENT_64B in various places to guard code that is specific
to 64-bit server processors compliant with arch 2.x. Consolidate the
logic in a helper macro with an explicit name.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Tested-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/ppc.c | 2 +-
target/ppc/cpu.h | 6 ++++++
target/ppc/helper_regs.h | 2 +-
target/ppc/translate.c | 10 ++++------
4 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 49d57469fb..ad20584f26 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1101,7 +1101,7 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t
freq)
tb_env = g_malloc0(sizeof(ppc_tb_t));
env->tb_env = tb_env;
tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
- if (env->insns_flags & PPC_SEGMENT_64B) {
+ if (is_book3s_arch2x(env)) {
/* All Book3S 64bit CPUs implement level based DEC logic */
tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
}
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index fc12b4688e..0707177584 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2409,6 +2409,12 @@ enum {
target_ulong cpu_read_xer(CPUPPCState *env);
void cpu_write_xer(CPUPPCState *env, target_ulong xer);
+/*
+ * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
+ * have PPC_SEGMENT_64B.
+ */
+#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
+
static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h
index a2205e1044..c863abc0bf 100644
--- a/target/ppc/helper_regs.h
+++ b/target/ppc/helper_regs.h
@@ -152,7 +152,7 @@ static inline int hreg_store_msr(CPUPPCState *env,
target_ulong value,
* - 64-bit embedded implementations do not need any operation to be
* performed when PR is set.
*/
- if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {
+ if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
}
#endif
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d3aaa6482c..576210d901 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3755,7 +3755,7 @@ static void gen_bcond(DisasContext *ctx, int type)
* arch 2.x, do implement a "test and decrement" logic instead,
* as described in their respective UMs.
*/
- if (unlikely(!(ctx->insns_flags & PPC_SEGMENT_64B))) {
+ if (unlikely(!is_book3s_arch2x(ctx))) {
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
tcg_temp_free(temp);
tcg_temp_free(target);
@@ -3913,7 +3913,7 @@ static void gen_rfi(DisasContext *ctx)
/* This instruction doesn't exist anymore on 64-bit server
* processors compliant with arch 2.x
*/
- if (ctx->insns_flags & PPC_SEGMENT_64B) {
+ if (is_book3s_arch2x(ctx)) {
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
return;
}
@@ -6535,8 +6535,7 @@ static void gen_msgclr(DisasContext *ctx)
GEN_PRIV;
#else
CHK_HV;
- /* 64-bit server processors compliant with arch 2.x */
- if (ctx->insns_flags & PPC_SEGMENT_64B) {
+ if (is_book3s_arch2x(ctx)) {
gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
} else {
gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
@@ -6550,8 +6549,7 @@ static void gen_msgsnd(DisasContext *ctx)
GEN_PRIV;
#else
CHK_HV;
- /* 64-bit server processors compliant with arch 2.x */
- if (ctx->insns_flags & PPC_SEGMENT_64B) {
+ if (is_book3s_arch2x(ctx)) {
gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
} else {
gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
--
2.20.1
- [Qemu-ppc] [PULL 0/8] ppc-for-4.0 queue 20190329, David Gibson, 2019/03/28
- [Qemu-ppc] [PULL 3/8] target/ppc: Consolidate 64-bit server processor detection in a helper,
David Gibson <=
- [Qemu-ppc] [PULL 2/8] target/ppc: Enable "decrement and test CTR" version of bcctr, David Gibson, 2019/03/28
- [Qemu-ppc] [PULL 5/8] target/ppc: Fix QEMU crash with stxsdx, David Gibson, 2019/03/28
- [Qemu-ppc] [PULL 8/8] exec: Only count mapped memory backends for qemu_getrampagesize(), David Gibson, 2019/03/28
- [Qemu-ppc] [PULL 7/8] spapr/irq: Add XIVE sanity checks on non-P9 machines, David Gibson, 2019/03/28
- [Qemu-ppc] [PULL 6/8] spapr: Simplify handling of host-serial and host-model values, David Gibson, 2019/03/28
- [Qemu-ppc] [PULL 4/8] target/ppc: Improve comment of bcctr used for spectre v2 mitigation, David Gibson, 2019/03/28
- [Qemu-ppc] [PULL 1/8] target/ppc: Fix TCG temporary leaks in gen_bcond(), David Gibson, 2019/03/28